serial: of: add a PORT_RT2880 definition
The Ralink RT2880 SoC and its successors have an internal 8250 core. This core
needs the same quirks applied as the AMD AU1xxx uart. In addition to these
quirks, the ports memory region is only 0x100 unlike the AU1xxx which has a
size of 0x1000.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 7e78f30..2235032 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2640,8 +2640,11 @@
static unsigned int serial8250_port_size(struct uart_8250_port *pt)
{
- if (pt->port.iotype == UPIO_AU)
+ if (pt->port.iotype == UPIO_AU) {
+ if (pt->port.type == PORT_RT2880)
+ return 0x100;
return 0x1000;
+ }
if (is_omap1_8250(pt))
return 0x16 << pt->port.regshift;
diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
index 9c64ad2..8749fb8 100644
--- a/drivers/tty/serial/of_serial.c
+++ b/drivers/tty/serial/of_serial.c
@@ -130,8 +130,15 @@
port->dev = &ofdev->dev;
- if (type == PORT_TEGRA)
+ switch (type) {
+ case PORT_TEGRA:
port->handle_break = tegra_serial_handle_break;
+ break;
+
+ case PORT_RT2880:
+ port->iotype = UPIO_AU;
+ break;
+ }
return 0;
out:
@@ -317,6 +324,7 @@
{ .compatible = "ns16850", .data = (void *)PORT_16850, },
{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
+ { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
{ .compatible = "altr,16550-FIFO32",
.data = (void *)PORT_ALTR_16550_F32, },
{ .compatible = "altr,16550-FIFO64",