/*
 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
 *
 * Author: Youngmin Nam <youngmin.nam@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Device Tree binding constants for Exynos9810 interrupt controller.
*/

#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_9820_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_9820_H

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define INTREQ__NOTIFY	0
#define INTREQ__RTC_ALARM_INT	1
#define INTREQ__RTC_TIC_INT_0	2
#define INTREQ__TOP_RTC_ALARM_INT	3
#define INTREQ__TOP_RTC_TIC_INT_0	4
#define INTREQ__ALIVE_EINT0	5
#define INTREQ__ALIVE_EINT1	6
#define INTREQ__ALIVE_EINT2	7
#define INTREQ__ALIVE_EINT3	8
#define INTREQ__ALIVE_EINT4	9
#define INTREQ__ALIVE_EINT5	10
#define INTREQ__ALIVE_EINT6	11
#define INTREQ__ALIVE_EINT7	12
#define INTREQ__ALIVE_EINT8	13
#define INTREQ__ALIVE_EINT9	14
#define INTREQ__ALIVE_EINT10	15
#define INTREQ__ALIVE_EINT11	16
#define INTREQ__ALIVE_EINT12	17
#define INTREQ__ALIVE_EINT13	18
#define INTREQ__ALIVE_EINT14	19
#define INTREQ__ALIVE_EINT15	20
#define INTREQ__ALIVE_EINT16	21
#define INTREQ__ALIVE_EINT17	22
#define INTREQ__ALIVE_EINT18	23
#define INTREQ__ALIVE_EINT19	24
#define INTREQ__ALIVE_EINT20	25
#define INTREQ__ALIVE_EINT21	26
#define INTREQ__ALIVE_EINT22	27
#define INTREQ__ALIVE_EINT23	28
#define INTREQ__ALIVE_EINT24	29
#define INTREQ__ALIVE_EINT25	30
#define INTREQ__ALIVE_EINT26	31
#define INTREQ__ALIVE_EINT27	32
#define INTREQ__ALIVE_EINT28	33
#define INTREQ__ALIVE_EINT29	34
#define INTREQ__ALIVE_EINT30	35
#define INTREQ__ALIVE_EINT31	36
#define INTREQ__ALIVE_EINT32	37
#define INTREQ__ALIVE_EINT33	38
#define INTREQ__MAILBOX_DBGCORE2AP	39
#define INTREQ__MAILBOX_APM2AP	40
#define INTREQ__MAILBOX_CP2AP	41
#define INTREQ__S_MAILBOX_CP2AP	42
#define INTREQ__SPEEDY_APM	43
#define INTREQ__SPEEDY_SUB_APM	44
#define INTREQ__RFMSPEEDY_APM	45
#define INTREQ__AUD_ABOX_GIC400	46
#define INTREQ__AUD_PPMU_UPPER_NORMAL	47
#define INTREQ__AUD_SMMU_NONSECURE	48
#define INTREQ__AUD_TREX_DEBUG	49
#define INTREQ__AUD_SMMU_SECURE	50
#define INTREQ__AUD_WDT	51
#define INTREQ__TREX_D0_DEBUG	52
#define INTREQ__TREX_D1_DEBUG	53
#define INTREQ__TREX_P_DEBUG	54
#define INTREQ__TREX_RB_DEBUG	55
#define INTREQ__TREX_PPMU_BUSCDP	56
#define INTREQ__TREX_PPMU_SBIC	57
#define INTREQ__TREX_PPMU_SIREX	58
#define INTREQ__TREX_PPMU_IVASC	59
#define INTREQ__TREX_PPMU_AVPS	60
#define INTREQ__TREX_P_PPMU_CORE_BUSC	61
#define INTREQ__PPFW	62
#define INTREQ__SPDMA	63
#define INTREQ__PDMA0	64
#define INTREQ__SBIC	65
#define INTREQ__DIT_TxEnd	66
#define INTREQ__DIT_RxEnd	67
#define INTREQ__DIT_BusErr	68
#define INTREQ__TREX_PPMU_BUSCS0	69
#define INTREQ__TREX_PPMU_BUSCS1	70
#define INTREQ__TREX_PPMU_BUSCS2	71
#define INTREQ__TREX_PPMU_BUSCS3	72
#define INTREQ__MMCACHE	73
#define INTREQ__MMCACHE_PPFW	74
#define INTREQ__TREX_PPMU_DIT	75
#define INTREQ__USI_CMGP0	76
#define INTREQ__I2C_CMGP0	77
#define INTREQ__USI_CMGP1	78
#define INTREQ__I2C_CMGP1	79
#define INTREQ__USI_CMGP2	80
#define INTREQ__I2C_CMGP2	81
#define INTREQ__USI_CMGP3	82
#define INTREQ__I2C_CMGP3	83
#define INTREQ__ADC_CMGP2AP	84
#define INTREQ__EXT_INTM0_0	85
#define INTREQ__EXT_INTM0_1	86
#define INTREQ__EXT_INTM0_2	87
#define INTREQ__EXT_INTM0_3	88
#define INTREQ__EXT_INTM0_4	89
#define INTREQ__EXT_INTM0_5	90
#define INTREQ__EXT_INTM0_6	91
#define INTREQ__EXT_INTM0_7	92
#define INTREQ__EXT_INTM0_8	93
#define INTREQ__EXT_INTM0_9	94
#define INTREQ__EXT_INTM1_0	95
#define INTREQ__EXT_INTM1_1	96
#define INTREQ__EXT_INTM1_2	97
#define INTREQ__EXT_INTM1_3	98
#define INTREQ__EXT_INTM1_4	99
#define INTREQ__EXT_INTM1_5	100
#define INTREQ__EXT_INTM1_6	101
#define INTREQ__EXT_INTM1_7	102
#define INTREQ__EXT_INTM1_8	103
#define INTREQ__EXT_INTM1_9	104
#define INTREQ__EXT_INTM2_0	105
#define INTREQ__EXT_INTM2_1	106
#define INTREQ__EXT_INTM2_2	107
#define INTREQ__EXT_INTM2_3	108
#define INTREQ__EXT_INTM2_4	109
#define INTREQ__EXT_INTM2_5	110
#define INTREQ__EXT_INTM2_6	111
#define INTREQ__EXT_INTM2_7	112
#define INTREQ__EXT_INTM2_8	113
#define INTREQ__EXT_INTM2_9	114
#define INTREQ__EXT_INTM3_0	115
#define INTREQ__EXT_INTM3_1	116
#define INTREQ__PPC_DEBUG_CCI_PPC_INTR	117
#define INTREQ__CCI_ERRINT	118
#define INTREQ__CCI_ERRFATAL	119
#define INTREQ__BDU_O_INT_PSCDC	120
#define INTREQ__TREX_D_CORE_debugInterrupt	121
#define INTREQ__TREX_D_CORE_ppcInterrupt_IRPS0	122
#define INTREQ__TREX_D_CORE_ppcInterrupt_IRPS1	123
#define INTREQ__TREX_D_CORE_ppcInterrupt_CP0	124
#define INTREQ__TREX_D_CORE_ppcInterrupt_CP1	125
#define INTREQ__TREX_D_CORE_ppcInterrupt_CORE_DP	126
#define INTREQ__TREX_P0_CORE_debugInterrupt	127
#define INTREQ__TREX_P1_CORE_debugInterrupt	128
#define INTREQ__TREX_P1_CORE_ppcInterrupt_CORE_P0P1	129
#define INTREQ__PPMU_CPUCL0_0_O_interrupt_upper_or_normal	130
#define INTREQ__PPMU_CPUCL0_0_O_interrupt_lower	131
#define INTREQ__PPMU_CPUCL0_1_O_interrupt_upper_or_normal	132
#define INTREQ__PPMU_CPUCL0_1_O_interrupt_lower	133
#define INTREQ__PPMU_CPUCL2_0_O_interrupt_upper_or_normal	134
#define INTREQ__PPMU_CPUCL2_0_O_interrupt_lower	135
#define INTREQ__PPMU_CPUCL2_1_O_interrupt_upper_or_normal	136
#define INTREQ__PPMU_CPUCL2_1_O_interrupt_lower	137
#define INTREQ__PPFW_G3D_INTERRUPT	138
#define INTREQ__CCI_TZCINT	139
#define INTREQ__PPCFW_G3D_INT	140
#define INTREQ__CPUCL0_PMUIRQ_0	141
#define INTREQ__CPUCL0_PMUIRQ_1	142
#define INTREQ__CPUCL0_PMUIRQ_2	143
#define INTREQ__CPUCL0_PMUIRQ_3	144
#define INTREQ__CPUCL0_PMUIRQ_4	145
#define INTREQ__CPUCL0_PMUIRQ_5	146
#define INTREQ__CPUCL0_CLUSTERPMUIRQ	147
#define INTREQ__CPUCL0_CTIIRQ_0	148
#define INTREQ__CPUCL0_CTIIRQ_1	149
#define INTREQ__CPUCL0_CTIIRQ_2	150
#define INTREQ__CPUCL0_CTIIRQ_3	151
#define INTREQ__CPUCL0_CTIIRQ_4	152
#define INTREQ__CPUCL0_CTIIRQ_5	153
#define INTREQ__CPUCL0_COMMIRQ_0	154
#define INTREQ__CPUCL0_COMMIRQ_1	155
#define INTREQ__CPUCL0_COMMIRQ_2	156
#define INTREQ__CPUCL0_COMMIRQ_3	157
#define INTREQ__CPUCL0_COMMIRQ_4	158
#define INTREQ__CPUCL0_COMMIRQ_5	159
#define INTREQ__CPUCL0_ERRIRQ_0	160
#define INTREQ__CPUCL0_ERRIRQ_1	161
#define INTREQ__CPUCL0_ERRIRQ_2	162
#define INTREQ__CPUCL0_ERRIRQ_3	163
#define INTREQ__CPUCL0_ERRIRQ_4	164
#define INTREQ__CPUCL0_ERRIRQ_5	165
#define INTREQ__CPUCL0_ERRIRQ_6	166
#define INTREQ__CPUCL0_FAULTIRQ_0	167
#define INTREQ__CPUCL0_FAULTIRQ_1	168
#define INTREQ__CPUCL0_FAULTIRQ_2	169
#define INTREQ__CPUCL0_FAULTIRQ_3	170
#define INTREQ__CPUCL0_FAULTIRQ_4	171
#define INTREQ__CPUCL0_FAULTIRQ_5	172
#define INTREQ__CPUCL0_FAULTIRQ_6	173
#define INTREQ__CPUCL2_PMUIRQ_0	174
#define INTREQ__CPUCL2_PMUIRQ_1	175
#define INTREQ__CPUCL2_CTIIRQ_0	176
#define INTREQ__CPUCL2_CTIIRQ_1	177
#define INTREQ__CPUCL2_COMMIRQ_0	178
#define INTREQ__CPUCL2_COMMIRQ_1	179
#define INTREQ__CPUCL2_EXTERRIRQ	180
#define INTREQ__CPUCL2_INTERRIRQ	181
#define INTREQ__CPUCL2_GCUIRQ	182
#define INTREQ__DPU_DECON0_FRAME_START	183
#define INTREQ__DPU_DECON0_FRAME_DONE	184
#define INTREQ__STR_0	185
#define INTREQ__STR_1	186
#define INTREQ__DPU_DECON0_DQE_DIMMING_START	187
#define INTREQ__DPU_DECON0_DQE_DIMMING_END	188
#define INTREQ__DPU_DECON0_EXTRA	189
#define INTREQ__DPU_DSIM0	190
#define INTREQ__DPU_DSIM1	191
#define INTREQ__DPU_DECON1_FRAME_START	192
#define INTREQ__DPU_DECON1_FRAME_DONE	193
#define INTREQ__DPU_DECON1_EXTRA	194
#define INTREQ__DPU_DECON2_FRAME_START	195
#define INTREQ__DPU_DECON2_FRAME_DONE	196
#define INTREQ__DPU_DECON2_EXTRA	197
#define INTREQ__DPU_DMA_GF0	198
#define INTREQ__DPU_DMA_GF1	199
#define INTREQ__DPU_DMA_VG	200
#define INTREQ__DPU_DMA_VGS	201
#define INTREQ__DPU_DMA_VGF	202
#define INTREQ__DPU_DMA_VGRFS	203
#define INTREQ__DPU_DMA_WB	204
#define INTREQ__DPU_DPP_GF0	205
#define INTREQ__DPU_DPP_GF1	206
#define INTREQ__DPU_DPP_VG	207
#define INTREQ__DPU_DPP_VGF	208
#define INTREQ__DPU_DPP_VGS	209
#define INTREQ__DPU_DPP_VGRFS	210
#define INTREQ__SYSMMU_DPUD0_SECURE	211
#define INTREQ__SYSMMU_DPUD0_NONSECURE	212
#define INTREQ__SYSMMU_DPUD1_SECURE	213
#define INTREQ__SYSMMU_DPUD1_NONSECURE	214
#define INTREQ__SYSMMU_DPUD2_SECURE	215
#define INTREQ__SYSMMU_DPUD2_NONSECURE	216
#define INTREQ__PPMU_DPUD0_UPPER_OR_NORMAL	217
#define INTREQ__PPMU_DPUD1_UPPER_OR_NORMAL	218
#define INTREQ__PPMU_DPUD2_UPPER_OR_NORMAL	219
#define INTREQ__BLK_DSPM_SCORE_TS_II_o_INTERRUPT_TO_CPU	220
#define INTREQ__BLK_DSPM_PPMU_DSPM0_O_interrupt_upper_or_normal	221
#define INTREQ__BLK_DSPM_PPMU_DSPM1_O_interrupt_upper_or_normal	226
#define INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_NONSECURE	227
#define INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_SECURE	228
#define INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_NONSECURE	229
#define INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_SECURE	230
#define INTREQ__PPMU_FSYS0_UPPER_OR_NORMAL	231
#define INTREQ__SYSMMU_PCIE_GEN3A_NS	232
#define INTREQ__SYSMMU_PCIE_GEN3A_S	233
#define INTREQ__SYSMMU_PCIE_GEN3B_NS	234
#define INTREQ__SYSMMU_PCIE_GEN3B_S	235
#define INTREQ__PCIE_GEN3A	236
#define INTREQ__PCIE_IA_GEN3A	237
#define INTREQ__PCIE_GEN3B	238
#define INTREQ__PCIE_IA_GEN3B	239
#define INTREQ__GPIO_FSYS0	240
#define INTREQ__USB31DRD_GIC_0	241
#define INTREQ__USB31DRD_GIC_1	242
#define INTREQ__USB31DRD_FSVMINUS_GIC	243
#define INTREQ__USB31DRD_FSVPLUS_GIC	244
#define INTREQ__USB2_REMOTE_WAKEUP_GIC	245
#define INTREQ__USB2_REMOTE_CONNECT_GIC	246
#define INTREQ__USB2_REMOTE_TIMER_GIC	247
#define INTREQ__DP_LINK	248
#define INTREQ__UFS_EMBD	249
#define INTREQ__MMC_CARD	250
#define INTREQ__GPIO_FSYS1	251
#define INTREQ__PPMU_FSYS1_UPPER_OR_NORMAL	252
#define INTREQ__PCIE_WIFI0	253
#define INTREQ__PCIE_IA_WIFI0	254
#define INTREQ__RTIC	255
#define INTREQ__SSS_SWDT2	256
#define INTREQ__SSS_SWDT1	257
#define INTREQ__SSS_KM	258
#define INTREQ__SSS_S_MB	259
#define INTREQ__SSS_NS_MB	260
#define INTREQ__SSS	261
#define INTREQ__UFS_CARD	262
#define INTREQ__SYSMMU_FSYS1_NS	263
#define INTREQ__SYSMMU_FSYS1_S	264
#define INTREQ__JSQZ	265
#define INTREQ__G2D	266
#define INTREQ__JPEG	267
#define INTREQ__MSCL	268
#define INTREQ__ASTC	269
#define INTREQ__PPMU_G2DD0_interrupt_upper_or_normal	270
#define INTREQ__PPMU_G2DD1_interrupt_upper_or_normal	271
#define INTREQ__PPMU_G2DD2_interrupt_upper_or_normal	272
#define INTREQ__SYSMMU_G2DD0_interrupt_nonsecure	273
#define INTREQ__SYSMMU_G2DD0_interrupt_secure	274
#define INTREQ__SYSMMU_G2DD1_interrupt_nonsecure	275
#define INTREQ__SYSMMU_G2DD1_interrupt_secure	276
#define INTREQ__SYSMMU_G2DD2_interrupt_nonsecure	277
#define INTREQ__SYSMMU_G2DD2_interrupt_secure	278
#define INTREQ__PPMU_G3D0_O_interrupt_upper_or_normal	279
#define INTREQ__PPMU_G3D0_O_interrupt_lower	280
#define INTREQ__PPMU_G3D1_O_interrupt_upper_or_normal	281
#define INTREQ__PPMU_G3D1_O_interrupt_lower	282
#define INTREQ__PPMU_G3D2_O_interrupt_upper_or_normal	283
#define INTREQ__PPMU_G3D2_O_interrupt_lower	284
#define INTREQ__PPMU_G3D3_O_interrupt_upper_or_normal	285
#define INTREQ__PPMU_G3D3_O_interrupt_lower	286
#define INTREQ__G3D_IRQMMU	287
#define INTREQ__G3D_IRQJOB	288
#define INTREQ__G3D_IRQGPU	289
#define INTREQ__G3D_IRQEVENT	290
#define INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_NONSECURE	291
#define INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_SECURE	292
#define INTREQ__BLK_ISPHQ_PPMU_ISPHQ_O_interrupt_upper_or_normal	293
#define INTREQ__BLK_ISPHQ_ISPHQ_INTREQ_0	294
#define INTREQ__BLK_ISPHQ_ISPHQ_INTREQ_1	295
#define INTREQ__ISPLP_0	296
#define INTREQ__ISPLP_1	297
#define INTREQ__GDC	298
#define INTREQ__MC_SCALER_0	299
#define INTREQ__MC_SCALER_1	300
#define INTREQ__SYSMMU_ISPLP0_NONSECURE	301
#define INTREQ__SYSMMU_ISPLP0_SECURE	302
#define INTREQ__SYSMMU_ISPLP1_NONSECURE	303
#define INTREQ__SYSMMU_ISPLP1_SECURE	304
#define INTREQ__PPMU_ISPLP0_UPPER_NORMAL	305
#define INTREQ__PPMU_ISPLP1_UPPER_NORMAL	306
#define INTREQ__VPP_0	307
#define INTREQ__VPP_1	308
#define INTREQ__CSIS0	309
#define INTREQ__CSIS1	310
#define INTREQ__CSIS2	311
#define INTREQ__CSIS3	312
#define INTREQ__PDP_CORE_TOP	313
#define INTREQ__PPMU_VRA2_UPPER	314
#define INTREQ__CSISX4_PDP_DMA0	315
#define INTREQ__CSISX4_PDP_DMA1	316
#define INTREQ__CSISX4_PDP_DMA2	317
#define INTREQ__CSISX4_PDP_DMA3	318
#define INTREQ__TAA0_0	319
#define INTREQ__TAA0_1	320
#define INTREQ__TAA1_0	321
#define INTREQ__TAA1_1	322
#define INTREQ__SYSMMU_ISPPRE_NONSECURE	323
#define INTREQ__SYSMMU_ISPPRE_SECURE	324
#define INTREQ__PPMU_ISPPRE_UPPER_NORMAL	325
#define INTREQ__PDP_TOP_DMA0	326
#define INTREQ__PDP_TOP_DMA1	327
#define INTREQ__PDP_TOP_DMA2	328
#define INTREQ__PDP_TOP_DMA3	329
#define INTREQ__CSIS3_1	330
#define INTREQ__BLK_IVA_IVA_iva_ap_irq_aq_0	331
#define INTREQ__BLK_IVA_IVA_iva_ap_irq_aq_1	332
#define INTREQ__BLK_IVA_PPMU_IVA_O_interrupt_upper_or_normal	333
#define INTREQ__BLK_IVA_SYSMMU_IVA_O_INTERRUPT_NONSECURE	334
#define INTREQ__BLK_IVA_SYSMMU_IVA_O_INTERRUPT_SECURE	335
#define INTREQ__BLK_IVA_TREX_RB1_IVA_o_ppcInterrupt	336
#define INTREQ__BLK_IVA_TREX_RB1_IVA_o_debugInterrupt	337
#define INTREQ__MFC	338
#define INTREQ__WFD	339
#define INTREQ__PPMU_MFCD0_interrupt_upper_or_normal	340
#define INTREQ__PPMU_MFCD1_interrupt_upper_or_normal	341
#define INTREQ__PPMU_MFCD2_interrupt_upper_or_normal	342
#define INTREQ__SYSMMU_MFCD0_interrupt_nonsecure	343
#define INTREQ__SYSMMU_MFCD0_interrupt_secure	344
#define INTREQ__SYSMMU_MFCD1_interrupt_nonsecure	345
#define INTREQ__SYSMMU_MFCD1_interrupt_secure	346
#define INTREQ__DMC_TZCINT_MIF0	347
#define INTREQ__DMC_TEMPERR_MIF0	348
#define INTREQ__DMC_TEMPHOT_MIF0	349
#define INTREQ__DMC_PPMPINT_R_MIF0	350
#define INTREQ__DMC_PPMPINT_W_MIF0	351
#define INTREQ__PPC_DVFS_U_MIF0	352
#define INTREQ__PPC_DVFS_L_MIF0	353
#define INTREQ__DMC_TZCINT_MIF1	354
#define INTREQ__DMC_TEMPERR_MIF1	355
#define INTREQ__DMC_TEMPHOT_MIF1	356
#define INTREQ__DMC_PPMPINT_R_MIF1	357
#define INTREQ__DMC_PPMPINT_W_MIF1	358
#define INTREQ__PPC_DVFS_U_MIF1	359
#define INTREQ__PPC_DVFS_L_MIF1	360
#define INTREQ__DMC_TZCINT_MIF2	361
#define INTREQ__DMC_TEMPERR_MIF2	362
#define INTREQ__DMC_TEMPHOT_MIF2	363
#define INTREQ__DMC_PPMPINT_R_MIF2	364
#define INTREQ__DMC_PPMPINT_W_MIF2	365
#define INTREQ__PPC_DVFS_U_MIF2	366
#define INTREQ__PPC_DVFS_L_MIF2	367
#define INTREQ__DMC_TZCINT_MIF3	368
#define INTREQ__DMC_TEMPERR_MIF3	369
#define INTREQ__DMC_TEMPHOT_MIF3	370
#define INTREQ__DMC_PPMPINT_R_MIF3	371
#define INTREQ__DMC_PPMPINT_W_MIF3	372
#define INTREQ__PPC_DVFS_U_MIF3	373
#define INTREQ__PPC_DVFS_L_MIF3	374
#define INTREQ__CP2AP_WAKEUP	375
#define INTREQ__CP2AP_SFR_BUS_READY	376
#define INTREQ__CP2AP_TREX_CP	377
#define INTREQ__USI15_USI	378
#define INTREQ__USI15_I2C	379
#define INTREQ__GPIO_PERIC0	380
#define INTREQ__UART_DBG	381
#define INTREQ__USI00_USI	382
#define INTREQ__USI00_I2C	383
#define INTREQ__USI01_USI	384
#define INTREQ__USI01_I2C	385
#define INTREQ__USI02_USI	386
#define INTREQ__USI02_I2C	387
#define INTREQ__USI03_USI	388
#define INTREQ__USI03_I2C	389
#define INTREQ__USI04_USI	390
#define INTREQ__USI04_I2C	391
#define INTREQ__USI05_USI	392
#define INTREQ__USI05_I2C	393
#define INTREQ__PWM0	394
#define INTREQ__PWM1	395
#define INTREQ__PWM2	396
#define INTREQ__PWM3	397
#define INTREQ__PWM4	398
#define INTREQ__USI12_USI	399
#define INTREQ__USI12_I2C	400
#define INTREQ__USI13_USI	401
#define INTREQ__USI13_I2C	402
#define INTREQ__USI14_USI	403
#define INTREQ__USI14_I2C	404
#define INTREQ__USI16_I3C	405
#define INTREQ__I3C_PERIC1	406
#define INTREQ__GPIO_PERIC1	407
#define INTREQ__UART_BT	408
#define INTREQ__SPI_CAM0	409
#define INTREQ__I2C_CAM0	410
#define INTREQ__I2C_CAM1	411
#define INTREQ__I2C_CAM2	412
#define INTREQ__I2C_CAM3	413
#define INTREQ__USI06_USI	414
#define INTREQ__USI06_I2C	415
#define INTREQ__USI07_USI	416
#define INTREQ__USI07_I2C	417
#define INTREQ__USI08_USI	418
#define INTREQ__USI08_I2C	419
#define INTREQ__USI09_USI	420
#define INTREQ__USI09_I2C	421
#define INTREQ__USI10_USI	422
#define INTREQ__USI10_I2C	423
#define INTREQ__USI11_USI	424
#define INTREQ__USI11_I2C	425
#define INTREQ__USI16_USI	426
#define INTREQ__USI17_USI	427
#define INTREQ__USI17_I2C	428
#define INTREQ__VRA2	429
#define INTREQ__MAILBOX_AP_VTS	430
#define INTREQ__WDT_VTS	431
#define INTREQ__NPU0_0	432
#define INTREQ__NPU0_1	433
#define INTREQ__NPU0_2	434
#define INTREQ__NPU0_3	435
#define INTREQ__NPU0_4	436
#define INTREQ__NPU0_5	437
#define INTREQ__NPU0_6	438
#define INTREQ__NPU0_7	439
#define INTREQ__NPU0_8	440
#define INTREQ__NPU0_9	441
#define INTREQ__NPU0_10	442
#define INTREQ__NPU0_11	443
#define INTREQ__NPU0_12	444
#define INTREQ__NPU0_13	445
#define INTREQ__NPU0_14	446
#define INTREQ__NPU0_15	447
#define INTREQ__NPU0_16	448
#define INTREQ__NPU0_17	449
#define INTREQ__NPU0_18	450
#define INTREQ__NPU0_19	451
#define INTREQ__NPU0_20	452
#define INTREQ__NPU1	453
#define INTREQ__TREX_PPMU_DSPM0	455
#define INTREQ__TREX_PPMU_DSPM1	456
#define INTREQ__TREX_PPMU_IVA	457
#define INTREQ__CSISX4_PDP_RD	458
#define INTREQ__SYSMMU_VRA2_NON	459
#define INTREQ__SYSMMU_VRA2_SEC	460
#define INTREQ__OTP_CON_TOP	461
#define INTREQ__OTP_CON_BIRA	462
#define INTREQ__OTP_CON_BISR	463
#define INTREQ__WDT_CLUSTER0	464
#define INTREQ__WDT_CLUSTER2	465
#define INTREQ__MCT_G0	466
#define INTREQ__MCT_G1	467
#define INTREQ__MCT_G2	468
#define INTREQ__MCT_G3	469
#define INTREQ__MCT_L0	470
#define INTREQ__MCT_L1	471
#define INTREQ__MCT_L2	472
#define INTREQ__MCT_L3	473
#define INTREQ__MCT_L4	474
#define INTREQ__MCT_L5	475
#define INTREQ__MCT_L6	476
#define INTREQ__MCT_L7	477
#define INTREQ__TMU_TMU_TOP	478
#define INTREQ__TMU_TMU_SUB	479


#endif	/* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_9820_H */