tree 24a2347bd5f5620dd5ac6a7d9964029c13245231
parent f4a75d2eb7b1e2206094b901be09adb31ba63681
author Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 1353162142 +0100
committer Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 1353418448 +0100

clk: mvebu: add mvebu core clocks.

This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.

Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>