| commit | 8f2bf2ad9673e187b5c2956497003f60e0885e5d | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Mon Jan 25 21:15:47 2016 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Fri Jan 29 11:30:29 2016 +0100 |
| tree | edd676725c6047f1f58f46de2998e2b61c4d6f7e | |
| parent | 3ca2377b6fed7c3db0c064ea73327cc6895e175d [diff] |
clk: sunxi: rewrite sun8i-a23-mbus-clk using the simpler composite clk sun8i-a23-mbus-clk used sunxi's factors clk, which is nice for very complicated clocks, but is not really needed here. Convert sun8i-a23-mbus-clk to use clk_composite, as it is a gate + mux + divider. This makes the code easier to understand. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>