tree 2033d95a7a57f792856cc08e1bd77f01386c5ed6
parent 26584853a44c58f3d6ac7360d697a2ddcd1a3efa
author Catalin Marinas <catalin.marinas@arm.com> 1243688418 +0100
committer Catalin Marinas <catalin.marinas@arm.com> 1243688418 +0100

Fix the VFP handling on the Feroceon CPU

This CPU generates synchronous VFP exceptions in a non-standard way -
the FPEXC.EX bit set but without the FPSCR.IXE bit being set like in the
VFP subarchitecture 1 or just the FPEXC.DEX bit like in VFP
subarchitecture 2. The main problem is that the faulty instruction
(which needs to be emulated in software) will be restarted several times
(normally until a context switch disables the VFP). This patch ensures
that the VFP exception is treated as synchronous.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Nicolas Pitre <nico@cam.org>