tree 0d5ada4405b192bfa9e03017306f77ee9a81eae1
parent dc8797e39fca777217fd4cfc9c74a5337a3daa76
author Chen-Yu Tsai <wens@csie.org> 1500904738 +0800
committer Ulf Hansson <ulf.hansson@linaro.org> 1504094508 +0200

clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock

The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.

This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>