commit 7605b3906192a171e651076325b1ed1d5ea57ec9
author Ralf Baechle <ralf@linux-mips.org> Tue Mar 20 13:56:50 2007 +0000
committer Ralf Baechle <ralf@linux-mips.org> Sat Mar 24 17:01:49 2007 +0000
tree a86d308b36fda5297349691089a868208a5a9688
parent 83598f1cb06101e972b1f5aaf3408eb729622fa8

[MIPS] Fix pipeline hazard.

In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

include/asm-mips/hazards.h

diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 5007315..e50c77e 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -52,6 +52,7 @@
 	 _ehb
 	)
 ASMMACRO(irq_enable_hazard,
+	 _ehb
 	)
 ASMMACRO(irq_disable_hazard,
 	_ehb