tree 7251bee620c2ad802148502305496d5b63090c19
parent 33e34dc6ee2cb2cf2d50e65c5b825d9ebb8b9e66
author Jan Nikitenko <jan.nikitenko@gmail.com> 1178609545 -0700
committer Linus Torvalds <torvalds@woody.linux-foundation.org> 1178648116 -0700

au1550 SPI controller driver

Here is a driver for the Alchemy au1550 PSC (Programmable Serial
Controller) in SPI master mode.

It supports dma transfers using the Alchemy descriptor based dma controller
for 4-8 bits per word SPI transfers.  For 9-24 bits per word transfers, pio
irq based mode is used to avoid setup of dma channels from scratch on each
number of bits per word change.

Tested with au1550; this may also work on other MIPS Alchemy cpus, like
au1200/au1210/au1250.  Used extensively with SD card connected via SPI;
this handles 8.1MHz SPI clock transfers using dma without any problem (the
highest SPI clock freq possible with au1550 running on 324MHz).

The driver supports sharing of SPI bus by multiple devices.  All features
of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per
word in 4-24 range).

As the SPI clock of the controller depends on main input clock that shall
be configured externally, platform data structure for au1550 SPI controller
driver contains mainclk_hz attribute to define the input clock rate.  From
this value, dividers of the controller for SPI clock are set up for
required frequency.

Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com>

Whitespace and section fixups.  Remove partial workaround for platform
setup bug in dma_mask setup; it couldn't work with multiple controllers.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>