| commit | 62cedc4fde2d15b08e4502aa3fb2d9d798f3ccd8 | [log] [tgz] |
|---|---|---|
| author | Florian Fainelli <florian@openwrt.org> | Tue Jan 31 18:18:45 2012 +0100 |
| committer | John Crispin <blogic@openwrt.org> | Wed Aug 22 23:46:38 2012 +0200 |
| tree | fee5a50adcb7181d44bf4f3364d46883bc49dd35 | |
| parent | 91405eb69ee007ee854aa917e2a15e6ccede2cd1 [diff] |
MIPS: introduce CPU_R4K_CACHE_TLB R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>