tree 0e861218bdb25d0ad3f41aa569f89d0f56d59d18
parent 4539c24fe4f92c09ee668ef959d3e8180df619b9
author Stephen Warren <swarren@nvidia.com> 1305670357 -0600
committer Greg Kroah-Hartman <gregkh@suse.de> 1305849062 -0700

tty/serial: Fix break handling for PORT_TEGRA

When a break is received, Tegra's UART apparently fills the FIFO with
0 bytes. These must be drained so that they aren't interpreted as actual
data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs.

v2: Added FIXME comment to clear_rx_fifo

Originally-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>