/*
 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
 *              http://www.samsung.com
 *
 * Author: Sung-Hyun Na <sunghyun.na@samsung.com>
 *
 * Chip Abstraction Layer for USB PHY
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _PHY_EXYNOS_USBDP_GEN2_REG_H_
#define _PHY_EXYNOS_USBDP_GEN2_REG_H_

#define USBDP_COMBO_G2_BIT_MASK_1		0x1
#define USBDP_COMBO_G2_BIT_MASK_2		0x3
#define USBDP_COMBO_G2_BIT_MASK_3		0x7
#define USBDP_COMBO_G2_BIT_MASK_4		0xF
#define USBDP_COMBO_G2_BIT_MASK_5		0x1F
#define USBDP_COMBO_G2_BIT_MASK_6		0x3F
#define USBDP_COMBO_G2_BIT_MASK_7		0x7F
#define USBDP_COMBO_G2_BIT_MASK_8		0xFF
#define USBDP_COMBO_G2_BIT_MASK_9		0x1FF
#define USBDP_COMBO_G2_BIT_MASK_10		0x3FF
#define USBDP_COMBO_G2_BIT_MASK_11		0x7FF
#define USBDP_COMBO_G2_BIT_MASK_12		0xFFF
#define USBDP_COMBO_G2_BIT_MASK_13		0x1FFF
#define USBDP_COMBO_G2_BIT_MASK_14		0x3FFF
#define USBDP_COMBO_G2_BIT_MASK_15		0x7FFF
#define USBDP_COMBO_G2_BIT_MASK_16		0xFFFF
#define USBDP_COMBO_G2_BIT_MASK_17		0x1FFFF
#define USBDP_COMBO_G2_BIT_MASK_18		0x3FFFF
#define USBDP_COMBO_G2_BIT_MASK_19		0x7FFFF
#define USBDP_COMBO_G2_BIT_MASK_20		0xFFFFF
#define USBDP_COMBO_G2_BIT_MASK_21		0x1FFFFF
#define USBDP_COMBO_G2_BIT_MASK_22		0x3FFFFF
#define USBDP_COMBO_G2_BIT_MASK_23		0x7FFFFF
#define USBDP_COMBO_G2_BIT_MASK_24		0xFFFFFF
#define USBDP_COMBO_G2_BIT_MASK_25		0x1FFFFFF
#define USBDP_COMBO_G2_BIT_MASK_26		0x3FFFFFF
#define USBDP_COMBO_G2_BIT_MASK_27		0x7FFFFFF
#define USBDP_COMBO_G2_BIT_MASK_28		0xFFFFFFF
#define USBDP_COMBO_G2_BIT_MASK_29		0x1FFFFFFF
#define USBDP_COMBO_G2_BIT_MASK_30		0x3FFFFFFF
#define USBDP_COMBO_G2_BIT_MASK_31		0x7FFFFFFF
#define USBDP_COMBO_G2_BIT_MASK_32		0xFFFFFFFF

#define USBDP_COMBO_G2_BIT_MASK(_bw)		USBDP_COMBO_G2_BIT_MASK_##_bw

#define USBDP_COMBO_G2_REG_MSK(_pos, _B)	(USBDP_COMBO_G2_BIT_MASK(_B) << _pos)
#define USBDP_COMBO_G2_REG_CLR(_pos, _B)	~(USBDP_COMBO_G2_REG_MSK(_pos, _B))
#define USBDP_COMBO_G2_REG_SET(_val, _pos, _B)	((_val & USBDP_COMBO_G2_BIT_MASK(_B)) << _pos)
#define USBDP_COMBO_G2_REG_GET(_reg, _pos, _B)	((_reg & (USBDP_COMBO_G2_BIT_MASK(_B) << _pos)) >> _pos)

#define EXYNOS_USBDP_CMN_008_0020	(0x0020)
#define USBDP_CMN_008_ANA_AUX_TX_TERM_MASK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_008_ANA_AUX_TX_TERM_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_008_ANA_AUX_TX_TERM_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_008_ANA_AUX_RX_TERM_MASK		USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_008_ANA_AUX_RX_TERM_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_008_ANA_AUX_RX_TERM_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_CMN_00E_0038	(0x0038)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_MAN_BSEL_M_MASK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_MAN_BSEL_M_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_MAN_BSEL_M_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_STB_NUM_MASK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_STB_NUM_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_00E_ANA_LCPLL_AFC_STB_NUM_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_CMN_014_0050	(0x0050)
#define USBDP_CMN_014_ANA_LCPLL_AVC_CNT_RUN_NUM_MASK			USBDP_COMBO_G2_REG_MSK(0, 6)
#define USBDP_CMN_014_ANA_LCPLL_AVC_CNT_RUN_NUM_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 6)
#define USBDP_CMN_014_ANA_LCPLL_AVC_CNT_RUN_NUM_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 6)

#define EXYNOS_USBDP_CMN_015_0054	(0x0054)
#define USBDP_CMN_015_ANA_LCPLL_AVC_CNT_WAIT_NUM_MASK			USBDP_COMBO_G2_REG_MSK(2, 4)
#define USBDP_CMN_015_ANA_LCPLL_AVC_CNT_WAIT_NUM_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 4)
#define USBDP_CMN_015_ANA_LCPLL_AVC_CNT_WAIT_NUM_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 4)
#define USBDP_CMN_015_ANA_LCPLL_AVC_EN					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_015_ANA_LCPLL_AVC_FORCE_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_016_0058	(0x0058)
#define USBDP_CMN_016_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_MASK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_CMN_016_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_CMN_016_ANA_LCPLL_AVC_MAN_CAP_BIAS_CODE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_CMN_016_ANA_LCPLL_AVC_VCI_MAX_SEL_MASK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_CMN_016_ANA_LCPLL_AVC_VCI_MAX_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_CMN_016_ANA_LCPLL_AVC_VCI_MAX_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_CMN_017_005C	(0x005C)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MID_SEL_MASK			USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MID_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MID_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MIN_SEL_MASK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MIN_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_CMN_017_ANA_LCPLL_AVC_VCI_MIN_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_CMN_R01D_0074	(0x0074)
#define USBDP_CMN_01D_LCPLL_ANA_LPF_R_SEL_FINE_MASK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_01D_LCPLL_ANA_LPF_R_SEL_FINE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_01D_LCPLL_ANA_LPF_R_SEL_FINE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_01D_ANA_LCPLL_ANA_VCI_SEL_MASK			USBDP_COMBO_G2_REG_MSK(1, 3)
#define USBDP_CMN_01D_ANA_LCPLL_ANA_VCI_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 1, 3)
#define USBDP_CMN_01D_ANA_LCPLL_ANA_VCI_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 1, 3)
#define USBDP_CMN_01D_ANA_LCPLL_ANA_VIC_TEST_EN_MASK			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R024_0090	(0x0090)
#define USBDP_CMN_024_ANA_LCPLL_PMS_MDIV_MASK				USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_024_ANA_LCPLL_PMS_MDIV_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_024_ANA_LCPLL_PMS_MDIV_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_CMN_R025_0094	(0x0094)
#define USBDP_CMN_025_ANA_LCPLL_PMS_MDIV_AFC_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_025_ANA_LCPLL_PMS_MDIV_AFC_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_025_ANA_LCPLL_PMS_MDIV_AFC_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_CMN_R031_00C4	(0x00C4)
#define USBDP_CMN_031_ANA_LCPLL_SDM_PH_NUM_SEL				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_031_ANA_LCPLL_SDM_PI_STEP_MASK			USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_CMN_031_ANA_LCPLL_SDM_PI_STEP_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_CMN_031_ANA_LCPLL_SDM_PI_STEP_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_CMN_031_ANA_LCPLL_SDC_N_MASK				USBDP_COMBO_G2_REG_MSK(1, 3)
#define USBDP_CMN_031_ANA_LCPLL_SDC_N_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 1, 3)
#define USBDP_CMN_031_ANA_LCPLL_SDC_N_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 1, 3)
#define USBDP_CMN_031_ANA_LCPLL_SDC_N2					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R038_00E0	(0x00E0)
#define USBDP_CMN_038_ANA_LCPLL_CD_TX_SER_RATE_SEL			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_038_ANA_LCPLL_CD_HSCLK_INV				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_038_ANA_LCPLL_CD_HSCLK_WEST_EN			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_038_ANA_LCPLL_CD_HSCLK_EAST_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_038_OVRD_LCPLL_CD_VREG_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_038_LCPLL_CD_VREG_EN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_038_OVRD_LCPLL_CD_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_038_LCPLL_CD_VREG_LPF_BYPASS				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R041_0104	(0x0104)
#define USBDP_CMN_A0104_ANA_LCPLL_RSVD_MASK				USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A0104_ANA_LCPLL_RSVD_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A0104_ANA_LCPLL_RSVD_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 0, 8)
#define USBDP_CMN_R041_PLL_CD_DIV2_EN_WAST				USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_R041_PLL_CD_RSTN_SEL_WAST				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_R041_PLL_CD_HSCLK_WEST_CTRL_MASK			USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_CMN_R041_PLL_CD_HSCLK_WEST_CTRL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_CMN_R041_PLL_CD_HSCLK_WEST_CTRL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_CMN_R041_PLL_CD_DIV2_EN_EAST				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_R041_PLL_CD_RSTN_SEL_EAST				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_R041_PLL_CD_HSCLK_EAST_CTRL_MASK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_CMN_R041_PLL_CD_HSCLK_EAST_CTRL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_CMN_R041_PLL_CD_HSCLK_EAST_CTRL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_CMN_A00E8	(0x00E8)
#define USBDP_CMN_A00E8_ANA_LCPLL_CD_VREG_LAD_SEL_MASK			USBDP_COMBO_G2_REG_MSK(4, 3)
#define USBDP_CMN_A00E8_ANA_LCPLL_CD_VREG_LAD_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 3)
#define USBDP_CMN_A00E8_ANA_LCPLL_CD_VREG_LAD_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 3)
#define USBDP_CMN_A00E8_OVRD_LCPLL_USB_LANE_TX_CLK_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A00E8_LCPLL_USB_LANE_TX_CLK_EN			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A00E8_ANA_LCPLL_USB_TX_CLK_SEL_MASK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_CMN_A00E8_ANA_LCPLL_USB_TX_CLK_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_CMN_A00E8_ANA_LCPLL_USB_TX_CLK_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_CMN_A012C	(0x012C)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_COARSE_MASK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_COARSE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_COARSE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_FINE_MASK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_FINE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A012C_ROPLL_ANA_CPP_CTRL_FINE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_CMN_A0134	(0x0134)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_COARSE_MASK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_COARSE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_COARSE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_FINE_MASK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_FINE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A0134_ROPLL_ANA_LPF_R_SEL_FINE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_CMN_A015C	(0x015C)
#define USBDP_CMN_A015C_ROPLL_PMS_MDIV_RBR_MASK				USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A015C_ROPLL_PMS_MDIV_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A015C_ROPLL_PMS_MDIV_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A0174	(0x0174)
#define USBDP_CMN_A0174_ROPLL_PMS_MDIV_AFC_RBR_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A0174_ROPLL_PMS_MDIV_AFC_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A0174_ROPLL_PMS_MDIV_AFC_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A018C	(0x018C)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_RBR_MASK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_HBR_MASK				USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_HBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A018C_ROPLL_PMS_SDIV_HBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_CMN_A01AC	(0x01AC)
#define USBDP_CMN_A01AC_ROPLL_SDM_DENOM_RBR_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A01AC_ROPLL_SDM_DENOM_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A01AC_ROPLL_SDM_DENOM_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A01BC	(0x01BC)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_SP			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_SSP			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_RBR			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_HBR			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_HBR2			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A01BC_ROPLL_SDM_NUMERATOR_SIGN_HBR3			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A01C8	(0x01C8)
#define USBDP_CMN_A01C8_ROPLL_SDM_NUMERATOR_RBR_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A01C8_ROPLL_SDM_NUMERATOR_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A01C8_ROPLL_SDM_NUMERATOR_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A01F0	(0x01F0)
#define USBDP_CMN_A01F0_ROPLL_SDC_NUMERATOR_RBR_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A01F0_ROPLL_SDC_NUMERATOR_RBR_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A01F0_ROPLL_SDC_NUMERATOR_RBR_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A0208	(0x0208)
#define USBDP_CMN_A0208_ROPLL_SDC_DENOMINATOR_RBR_MASK			USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A0208_ROPLL_SDC_DENOMINATOR_RBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A0208_ROPLL_SDC_DENOMINATOR_RBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_COM_CMN_A021C	(0x021C)
#define USBDP_CMN_A021C_ANA_ROPLL_SSC_FM_DEVIATION_MASK			USBDP_COMBO_G2_REG_MSK(0, 6)
#define USBDP_CMN_A021C_ANA_ROPLL_SSC_FM_DEVIATION_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 6)
#define USBDP_CMN_A021C_ANA_ROPLL_SSC_FM_DEVIATION_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 6)

#define EXYNOS_USBDP_COM_CMN_A0220	(0x0220)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_FREQ_MASK			USBDP_COMBO_G2_REG_MSK(2, 5)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_FREQ_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 2, 5)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_FREQ_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 2, 5)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_PROF_OPT_MASK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_PROF_OPT_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_CMN_A0220_ANA_ROPLL_SSC_FM_PROF_OPT_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_CMN_A0228	(0x0228)
#define USBDP_CMN_A0228_ANA_ROPLL_CD_TX_SER_RATE_SEL			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_A0228_ANA_ROPLL_CD_HSCLK_INV				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A0228_ANA_ROPLL_CD_HSCLK_WEST_EN			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A0228_ANA_ROPLL_CD_HSCLK_EAST_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A0228_OVRD_ROPLL_CD_VREG_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0228_ROPLL_CD_VREG_EN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0228_OVRD_ROPLL_CD_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0228_ROPLL_CD_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(7, 1)

#define EXYNOS_USBDP_COM_CMN_A0230	(0x0230)
#define USBDP_CMN_A0230_ANA_ROPLL_CD_VREG_LAD_SEL_MASK			USBDP_COMBO_G2_REG_MSK(4, 3)
#define USBDP_CMN_A0230_ANA_ROPLL_CD_VREG_LAD_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 3)
#define USBDP_CMN_A0230_ANA_ROPLL_CD_VREG_LAD_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 3)
#define USBDP_CMN_A0230_OVRD_ROPLL_USB_LANE_TX_CLK_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0230_ROPLL_USB_LANE_TX_CLK_EN			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0230_ANA_ROPLL_USB_TX_CLK_SEL_MASK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_CMN_A0230_ANA_ROPLL_USB_TX_CLK_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_CMN_A0230_ANA_ROPLL_USB_TX_CLK_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_CMN_R093_248	(0x0248)
#define USBDP_CMN_A0248_ANA_ROPLL_RSVD_MASK				USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_CMN_A0248_ANA_ROPLL_RSVD_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_CMN_A0248_ANA_ROPLL_RSVD_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 0, 8)
#define USBDP_CMN_R093_PLL_CD_DIV2_EN_WAST				USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_R093_PLL_CD_RSTN_SEL_WAST				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_R093_PLL_CD_HSCLK_WEST_CTRL_MASK			USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_CMN_R093_PLL_CD_HSCLK_WEST_CTRL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_CMN_R093_PLL_CD_HSCLK_WEST_CTRL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_CMN_R093_PLL_CD_DIV2_EN_EAST				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_R093_PLL_CD_RSTN_SEL_EAST				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_R093_PLL_CD_HSCLK_EAST_CTRL_MASK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_CMN_R093_PLL_CD_HSCLK_EAST_CTRL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_CMN_R093_PLL_CD_HSCLK_EAST_CTRL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_CMN_A0258	(0x0258)
#define USBDP_CMN_A0258_OVRD_CMN_RATE					USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A0258_CMN_RATE_MASK					USBDP_COMBO_G2_REG_MSK(3, 2)
#define USBDP_CMN_A0258_CMN_RATE_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 3, 2)
#define USBDP_CMN_A0258_CMN_RATE_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 3, 2)
#define USBDP_CMN_A0258_CMN_LCPLL_ALONE_MODE				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0258_CMN_TIMER_SEL					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0258_PLL_LC12_RO34_GEN_SEL				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0288	(0x0288)
#define USBDP_CMN_A0288_LANE_MUX_SEL_DP_MASK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A0288_LANE_MUX_SEL_DP_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A0288_LANE_MUX_SEL_DP_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A0288_DP_LANE_EN_MASK					USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A0288_DP_LANE_EN_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A0288_DP_LANE_EN_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_CMN_A028C	(0x028C)
#define USBDP_CMN_A028C_DP_TX_LINK_BW_MASK				USBDP_COMBO_G2_REG_MSK(5, 2)
#define USBDP_CMN_A028C_DP_TX_LINK_BW_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 5, 2)
#define USBDP_CMN_A028C_DP_TX_LINK_BW_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 5, 2)
#define USBDP_CMN_A028C_OVRD_RX_CDR_DATA_MODE_EXIT			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A028C_RX_CDR_DATA_MODE_EXIT				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A028C_DP_TX_LANE_SWAP_EN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A028C_DP_TX_DATA_INV					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A028C_DP_TX_DATA_SWAP					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R00B4_02D0	(0x02D0)
#define USBDP_CMN_R00B4_CDR_LOCK_DELAY_CODE_MASK			USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_CMN_R00B4_CDR_LOCK_DELAY_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_CMN_R00B4_CDR_LOCK_DELAY_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_CMN_R00B4_RX_OC_DONE_DELAY_CODE_MASK			USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_CMN_R00B4_RX_OC_DONE_DELAY_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 2, 3)
#define USBDP_CMN_R00B4_RX_OC_DONE_DELAY_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 2, 3)
#define USBDP_CMN_R00B4_SSC_EN						USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0308	(0x0308)
#define USBDP_CMN_A0308_PCS_PM_STATE_MASK				USBDP_COMBO_G2_REG_MSK(4, 3)
#define USBDP_CMN_A0308_PCS_PM_STATE_SET(_x)				USBDP_COMBO_G2_REG_SET(_x, 4, 3)
#define USBDP_CMN_A0308_PCS_PM_STATE_GET(_R)				USBDP_COMBO_G2_REG_GET(_R, 4, 3)
#define USBDP_CMN_A0308_OVRD_PCS_BGR_EN					USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0308_PCS_BGR_EN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0308_OVRD_PCS_BIAS_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0308_PCS_BIAS_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A030C	(0x030C)
#define USBDP_CMN_A030C_OVRD_PCS_POWERDOWN				USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_A030C_PCS_POWERDOWN					USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A030C_OVRD_PCS_CDR_EN					USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A030C_PCS_CDR_EN					USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A030C_OVRD_PCS_CMN_RSTN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A030C_PCS_CMN_RSTN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A030C_OVRD_PCS_DES_EN					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A030C_PCS_DES_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0310	(0x0310)
#define USBDP_CMN_A0310_OVRD_PCS_INIT_RSTN				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A0310_PCS_INIT_RSTN					USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A0310_OVRD_PCS_LANE_RSTN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0310_PCS_LANE_RSTN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0310_OVRD_PCS_PLL_EN					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0310_PCS_PLL_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0314	(0x0314)
#define USBDP_CMN_A0314_OVRD_PCS_REF_FREQ_SEL				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A0314_PCS_REF_FREQ_SEL_MSK				USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_CMN_A0314_PCS_REF_FREQ_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_CMN_A0314_PCS_REF_FREQ_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_CMN_A0314_OVRD_PCS_RX_CTLE_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0314_PCS_RX_CTLE_EN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0314_OVRD_PCS_RX_DFE_ADAP_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0314_PCS_RX_DFE_ADAP_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0318	(0x0318)
#define USBDP_CMN_A0318_OVRD_PCS_TX_DRV_BEACON				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A0318_PCS_TX_DRV_BEACON				USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A0318_OVRD_PCS_TX_DRV_CM_KEEPER_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A0318_PCS_TX_DRV_CM_KEEPER_EN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A0318_OVRD_PCS_RX_TERM_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0318_PCS_RX_TERM_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A031C	(0x031C)
#define USBDP_CMN_A031C_OVRD_PCS_TX_DRV_BEACON				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A031C_PCS_TX_DRV_BEACON				USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A031C_OVRD_PCS_TX_DRV_CM_KEEPER_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A031C_PCS_TX_DRV_CM_KEEPER_EN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A031C_OVRD_PCS_TX_DRV_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A031C_PCS_TX_DRV_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0328	(0x0328)
#define USBDP_CMN_A0328_OVRD_PCS_TX_DRV_PRE_LVL_CTRL			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A0328_PCS_TX_DRV_PRE_LVL_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(2, 4)
#define USBDP_CMN_A0328_PCS_TX_DRV_PRE_LVL_CTRL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 2, 4)
#define USBDP_CMN_A0328_PCS_TX_DRV_PRE_LVL_CTRL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 2, 4)
#define USBDP_CMN_A0328_OVRD_PCS_TX_ELECIDLE				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0328_PCS_TX_ELECIDLE					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A032C	(0x032C)
#define USBDP_CMN_A032C_OVRD_PCS_TX_LPFS_EN				USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_A032C_PCS_TX_LPFS_EN					USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A032C_OVRD_PCS_RX_LPFS_EN				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_A032C_PCS_RX_LPFS_EN					USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_A032C_OVRD_PCS_TX_RCV_DET_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A032C_PCS_TX_RCV_DET_EN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A032C_OVRD_PCS_TX_SER_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A032C_PCS_TX_SER_EN					USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0350	(0x0350)
#define USBDP_CMN_A0350_ANA_LCPLL_LOCK_DONE				USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_CMN_A0350_ANA_LCPLL_AFC_DONE				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_L_MSK				USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_L_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_L_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_M_MSK				USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_M_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A0350_ANA_LCPLL_MON_AFC_M_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_CMN_A0354	(0x0354)
#define USBDP_CMN_A0354_ANA_LCPLL_MON_GM_CODE_MSK			USBDP_COMBO_G2_REG_MSK(2, 4)
#define USBDP_CMN_A0354_ANA_LCPLL_MON_GM_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 2, 4)
#define USBDP_CMN_A0354_ANA_LCPLL_MON_GM_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 2, 4)
#define USBDP_CMN_A0354_ANA_ROPLL_LOCK_DONE				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A0354_ANA_ROPLL_AFC_DONE				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A038C	(0x038C)
#define USBDP_CMN_A038C_DP_INIT_RSTN					USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_A038C_DP_CMN_RSTN					USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_CMN_A038C_CDR_WATCHDOG_EN					USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_A038C_CDR_WATCHDON_MASK_CDR_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R0EA_03A8	(0x03A8)
#define USBDP_CMN_R0EA_OVRD_LN1_TX_DRV_IUP_CTRL				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_CMN_R0EA_OVRD_LN1_TX_DRV_IDN_CTRL				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_CMN_R0EA_OVRD_LN3_TX_DRV_IUP_CTRL				USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_CMN_R0EA_OVRD_LN3_TX_DRV_IDN_CTRL				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_CMN_R0EA_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_CMN_R0EA_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_CMN_R0EA_TX_DRV_LFPS_MODE_IDRV_IUP_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_CMN_R0EB_03AC	(0x03AC)
#define USBDP_CMN_R0EV_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(1, 3)
#define USBDP_CMN_R0EV_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 3)
#define USBDP_CMN_R0EV_TX_DRV_LFPS_MODE_IDRV_IDN_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 1, 3)
#define USBDP_CMN_R0EB_CDR_WTD_MASK_CDR_AFC_RESTART			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_CMN_R207_081C	(0x081C)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IDN_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_IDRV_IUP_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 3)
#define USBDP_CMN_R207_LN0_ANA_TX_IDRV_VREF_SEL				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_CMN_R207_LN0_ANA_TX_DRV_ACCDRV_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A0830	(0x0830)
#define USBDP_CMN_A0830_LN0_ANA_TX_JEQ_EN_MSK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A0830_LN0_ANA_TX_JEQ_EN_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A0830_LN0_ANA_TX_JEQ_EN_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A0830_LN0_TX_JEQ_EVEN_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A0830_LN0_TX_JEQ_EVEN_CTRL_SP_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A0830_LN0_TX_JEQ_EVEN_CTRL_SP_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_TRSV_A085C	(0x085C)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_SP			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_SSP			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_RB			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_HBR			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_HBR2			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_LC_RO_CLK_SEL_HBR3			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_A085C_OVRD_LN0_TX_LANE_DCC_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_A085C_LN0_TX_LANE_DCC_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R0235_08CC	(0x08CC)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_MSK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_RBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R0235_LN0_RX_CDR_VCO_FREQ_BOOST_HBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R0244_0910	(0x0910)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_MF_FWD_CTRL_HBR3_MSK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_MF_FWD_CTRL_HBR3_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_MF_FWD_CTRL_HBR3_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_HF_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_HF_CTRL_SP_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R0244_LN0_RX_CTLE_I_HF_CTRL_SP_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R0644_1910	(0x1910)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_MF_FWD_CTRL_HBR3_MSK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_MF_FWD_CTRL_HBR3_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_MF_FWD_CTRL_HBR3_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_HF_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_HF_CTRL_SP_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R0644_LN2_RX_CTLE_I_HF_CTRL_SP_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R0251_0944	(0x0944)
#define USBDP_TRSV_R0251_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_MSK		USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_R0251_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_R0251_LN0_RX_DFE_OC_SA_EDGE_ODD_CODE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_TRSV_R0266_0998	(0x0998)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_RBR_MSK			USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_RBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_RBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_HBR_MSK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_HBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R0266_LN0_RX_DFE_VGA_RL_CTRL_HBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R0267_099C	(0x099C)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR2_MSK		USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR2_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR2_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR3_MSK		USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR3_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
#define USBDP_TRSV_R0267_LN0_RX_DFE_VGA_RL_CTRL_HBR3_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 3)
#define USBDP_TRSV_R0267_LN0_ANA_RX_DFE_VGA_PBIAS_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_R0267_LN0_ANA_RX_DFE_VGA_PBIAS_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_R0267_LN0_ANA_RX_DFE_VGA_PBIAS_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_TRSV_A09A4	(0x09A4)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_OFSP_CTRL			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_PATH_CTRL			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_SET(_x)	USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_ITAIL_CTRL_GET(_R)	USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_SW_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(2, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_SW_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_SW_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_A09A4_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_TRSV_R026A_09A8	(0x09A8)
#define USBDP_TRSV_R026A_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(5, 2)
#define USBDP_TRSV_R026A_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 2)
#define USBDP_TRSV_R026A_LN0_ANA_RX_RTERM_INCM_VCM_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 2)
#define USBDP_TRSV_R026A_OVRD_LN0_RX_RTERM_CM_PULLDN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_R026A_LN0_RX_RTERM_CM_PULLDN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R026A_OVRD_LN0_RX_RTERM_VCM_EN			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R026A_LN0_RX_RTERM_VCM_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_R026A_LN0_ANA_RX_SQ_VREF_820M_LPF_BYPASS		USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R274_09D0	(0x09D0)
#define USBDP_TRSV_R274_LN0_LPF_CTRL_LFPS_MSK				USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_R274_LN0_LPF_CTRL_LFPS_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_R274_LN0_LPF_CTRL_LFPS_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_DIV_SEL_MSK			USBDP_COMBO_G2_REG_MSK(3, 2)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_DIV_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 3, 2)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_DIV_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 3, 2)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_SEL_MSK				USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R274_LN0_CDR_CKDLY_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R027E_09F8	(0x09F8)
#define USBDP_TRSV_R027E_LN0_RX_SSLMS_HF_INIT_MSK			USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_R027E_LN0_RX_SSLMS_HF_INIT_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_R027E_LN0_RX_SSLMS_HF_INIT_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 5)

#define EXYNOS_USBDP_TRSV_R27F_09FC	(0x09FC)
#define USBDP_TRSV_R27F_LN0_RX_SSLMS_MF_INIT_MSK			USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_R27F_LN0_RX_SSLMS_MF_INIT_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_R27F_LN0_RX_SSLMS_MF_INIT_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 5)

#define EXYNOS_USBDP_TRSV_R028B_0A2C	(0x0A2C)
#define USBDP_TRSV_R028B_LN0_RX_SSLMS_ADPA_COEF_SEL8			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R028C_0A30	(0x0A30)
#define USBDP_TRSV_R0230_LN0_RX_SSLMS_ADPA_COEF_SEL7_0_MSK		USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_R0230_LN0_RX_SSLMS_ADPA_COEF_SEL7_0_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_R0230_LN0_RX_SSLMS_ADPA_COEF_SEL7_0_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 8)

#define EXYNOS_USBDP_TRSV_R2A2_0A88	(0x0A88)
#define USBDP_TRSV_R2A2_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_MSK		USBDP_COMBO_G2_REG_MSK(1, 4)
#define USBDP_TRSV_R2A2_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 4)
#define USBDP_TRSV_R2A2_LN0_RX_CDR_FBB_VCO_CNT_WAIT_NO_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 1, 4)
#define USBDP_TRSV_R2A2_LN0_RX_CDR_FBB_MAN_SEL				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R2A5_0A94	(0x0A94)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_PLL_MODE_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_PLL_MODE_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_PLL_MODE_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_FBB_COARSE_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_FBB_COARSE_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R2A5_LN0_RX_CDR_FBB_COARSE_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R2A6_0A98	(0x0A98)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_FINE_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_FINE_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_FINE_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_PLL_BW_DIFF_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_PLL_BW_DIFF_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R2A6_LN0_RX_CDR_FBB_PLL_BW_DIFF_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R02BE_0AF8	(0x0AF8)
#define USBDP_TRSV_R20BE_LN0_OVRD_RX_RCAL_COMP_OUT			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_R20BE_LN0_RX_RCAL_COMP_OUT				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_R20BE_LN0_OVRD_RX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_R20BE_LN0_RX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_R20BE_LN0_OVRD_TX_RCAL_RSTN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R20BE_LN0_TX_RCAL_RSTN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R20BE_LN0_TX_RCAL_UP_OPT_CODE_MSK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_R20BE_LN0_TX_RCAL_UP_OPT_CODE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_R20BE_LN0_TX_RCAL_UP_OPT_CODE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_TRSV_R02BF_0AFC	(0x0AFC)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_DN_OPT_CODE_MSK			USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_DN_OPT_CODE_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_DN_OPT_CODE_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_UP_CODE_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_UP_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R20BF_LN0_TX_RCAL_UP_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R02C0_0B00	(0x0B00)
#define USBDP_TRSV_R02C0_LN0_TX_RCAL_DN_CODE_MSK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R02C0_LN0_TX_RCAL_DN_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R02C0_LN0_TX_RCAL_DN_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R02C0_LN0_OVRD_TX_RCAL_COMP_OUT			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R02C0_LN0_TX_RCAL_COMP_OUT				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R02C0_LN0_OVRD_TX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_R02C0_LN0_TX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_A0B84	(0x0B84)
#define USBDP_TRSV_A0B84_LN0_MON_RX_CDR_AFC_DONE			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A0B84_LN0_MON_RX_CDR_CAL_DONE			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_A0B84_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE		USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_A0B84_LN0_MON_RX_CDR_LOCK_DONE			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R040C_1030	(0x1030)
#define USBDP_TRSV_R040C_LN1_ANA_TX_JEQ_EN_MSK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R040C_LN1_ANA_TX_JEQ_EN_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R040C_LN1_ANA_TX_JEQ_EN_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R040C_LN1_TX_JEQ_EVEN_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R040C_LN1_TX_JEQ_EVEN_CTRL_SP_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R040C_LN1_TX_JEQ_EVEN_CTRL_SP_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_TRSV_A105C	(0x105C)
#define USBDP_TRSV_A105C_OVRD_LN1_TX_SER_VREG_EN			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A105C_LN1_TX_SER_VREG_EN				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A105C_LN1_ANA_TX_SER_VREG_BYPASS			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_A105C_OVRD_LN1_TX_SER_VREG_LPF_BYPSS			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_A105C_LN1_TX_SER_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A105C_LN1_ANA_TX_SER_VREG_LADDER_SEL_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_A105C_LN1_ANA_TX_SER_VREG_LADDER_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_A105C_LN1_ANA_TX_SER_VREG_LADDER_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_COM_TRSV_A10B4	(0x10B4)
#define USBDP_TRSV_A10B4_LN1_RETIMEDLB_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_A10B4_LN1_BIST_DATA_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_A0a9c	(0x0a9c)
#define HI_FBB(_x)							USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define LO_FBB(_x)							USBDP_COMBO_G2_REG_SET(_x, 0, 4)

#define EXYNOS_USBDP_TRSV_R41E_1078	(0x1078)
#define USBDP_TRSV_R41E_LN0_RX_DFE_ADD_DIS				USBDP_COMBO_G2_REG_MSK(0, 1)
#define EXYNOS_USBDP_TRSV_R41E_2078	(0x2078)

#define EXYNOS_USBDP_TRSV_R607_181C	(0x181C)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IDN_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IDN_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IDN_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IUP_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IUP_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_IUP_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 3)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_IDRV_VREF_SEL			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_R607_LN2_ANA_TX_DRV_ACCDRV_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A1830	(0x1830)
#define USBDP_CMN_A1830_LN2_ANA_TX_JEQ_EN_MSK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A1830_LN2_ANA_TX_JEQ_EN_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A1830_LN2_ANA_TX_JEQ_EN_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A1830_LN2_TX_JEQ_EVEN_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A1830_LN2_TX_JEQ_EVEN_CTRL_SP_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A1830_LN2_TX_JEQ_EVEN_CTRL_SP_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_TRSV_A185C	(0x185C)
#define USBDP_TRSV_A185C_OVRD_LN2_TX_SER_VREG_EN			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A185C_LN2_TX_SER_VREG_EN				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A185C_LN2_ANA_TX_SER_VREG_BYPASS			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_A185C_OVRD_LN2_TX_SER_VREG_LPF_BYPSS			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_A185C_LN2_TX_SER_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A185C_LN2_ANA_TX_SER_VREG_LADDER_SEL_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_A185C_LN2_ANA_TX_SER_VREG_LADDER_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_A185C_LN2_ANA_TX_SER_VREG_LADDER_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R633_18CC	(0x18CC)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_MSK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_RBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R633_LN2_RX_CDR_VCO_FREQ_BOOST_HBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R665_1994	(0x1994)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SP_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SP_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SSP_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SSP_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R665_LN2_RX_DFE_VGA_RL_CTRL_SSP_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R666_1998	(0x1998)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_RBR_MSK			USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_RBR_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 3, 3)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_RBR_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 3, 3)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_HRB_MSK			USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_HRB_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R666_LN2_RX_DFE_VGA_RL_CTRL_HRB_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R667_199C	(0x199C)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB2_MSK			USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB2_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB2_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB3_MSK			USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB3_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
#define USBDP_TRSV_R667_LN2_RX_DFE_VGA_RL_CTRL_HRB3_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 3)
#define USBDP_TRSV_R667_LN2_ANA_RX_DFE_VGA_PBIAS_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_R667_LN2_ANA_RX_DFE_VGA_PBIAS_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_R667_LN2_ANA_RX_DFE_VGA_PBIAS_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_COM_TRSV_A19A4	(0x19A4)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_OFSP_CTRL			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_PATH_CTRL			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_ITAIL_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_ITAIL_CTRL_SET(_x)	USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_ITAIL_CTRL_GET(_R)	USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_SW_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(2, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_SW_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_SW_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 2, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_A19A4_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_TRSV_R66A_19A8	(0x19A8)
#define USBDP_TRSV_R66A_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(5, 2)
#define USBDP_TRSV_R66A_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 2)
#define USBDP_TRSV_R66A_LN2_ANA_RX_RTERM_INCM_VCM_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 5, 2)
#define USBDP_TRSV_R66A_OVRD_LN2_ANA_RX_RTERM_CM_PULLDN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_R66A_LN2_ANA_RX_RTERM_CM_PULLDN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R66A_OVRD_LN2_RX_RTERM_VCM_EN			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R66A_LN2_RX_RTERM_VCM_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_R66A_LN2_ANA_RX_SQ_VREF_BYP				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R674_19D0	(0x09D0)
#define USBDP_TRSV_R674_LN2_LPF_CTRL_LFPS_MSK				USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_R674_LN2_LPF_CTRL_LFPS_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_R674_LN2_LPF_CTRL_LFPS_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 5, 3)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_DIV_SEL_MSK			USBDP_COMBO_G2_REG_MSK(3, 2)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_DIV_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 3, 2)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_DIV_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 3, 2)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_SEL_MSK				USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_SEL_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_R674_LN2_CDR_CKDLY_SEL_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_TRSV_R67E_19F8	(0x19F8)
#define USBDP_TRSV_R67E_LN2_RX_SSLMS_HF_INIT_MSK			USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_R67E_LN2_RX_SSLMS_HF_INIT_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_R67E_LN2_RX_SSLMS_HF_INIT_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 5)

#define EXYNOS_USBDP_TRSV_R67F_19FC	(0x19FC)
#define USBDP_TRSV_R67F_LN2_RX_SSLMS_MF_INIT_MSK			USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_R67F_LN2_RX_SSLMS_MF_INIT_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_R67F_LN2_RX_SSLMS_MF_INIT_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 5)

#define EXYNOS_USBDP_TRSV_R68B_1A2C	(0x1A2C)
#define USBDP_TRSV_R68B_LN2_RX_SSLMS_ADPA_COEF_SEL8			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R6A2_1A88	(0x1A88)
#define USBDP_TRSV_R6A2_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_MSK		USBDP_COMBO_G2_REG_MSK(1, 4)
#define USBDP_TRSV_R6A2_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 4)
#define USBDP_TRSV_R6A2_LN2_RX_CDR_FBB_VCO_CNT_WAIT_NO_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 1, 4)
#define USBDP_TRSV_R6A2_LN2_RX_CDR_FBB_MAN_SEL				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R6A6_1A98	(0x1A98)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_FINE_CTRL_MSK			USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_FINE_CTRL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_FINE_CTRL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_PLL_BW_DIFF_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_PLL_BW_DIFF_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R6A6_LN2_RX_CDR_FBB_PLL_BW_DIFF_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R6BE_1AF8	(0x1AF8)
#define USBDP_TRSV_R6BE_LN2_OVRD_RX_RCAL_COMP_OUT			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_R6BE_LN2_RX_RCAL_COMP_OUT				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_R6BE_LN2_OVRD_RX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_R6BE_LN2_RX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_R6BE_LN2_OVRD_TX_RCAL_RSTN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R6BE_LN2_TX_RCAL_RSTN				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R6BE_LN2_TX_RCAL_UP_OPT_CODE_MSK			USBDP_COMBO_G2_REG_MSK(0, 2)
#define USBDP_TRSV_R6BE_LN2_TX_RCAL_UP_OPT_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_R6BE_LN2_TX_RCAL_UP_OPT_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 2)

#define EXYNOS_USBDP_TRSV_R6BF_1AFC	(0x1AFC)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_DN_OPT_CODE_MSK			USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_DN_OPT_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_DN_OPT_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 2)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_UP_CODE_MSK				USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_UP_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_R6BF_LN2_TX_RCAL_UP_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_TRSV_R6C0_1B00	(0x1B00)
#define USBDP_TRSV_R6C0_LN2_TX_RCAL_DN_CODE_MSK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_R6C0_LN2_TX_RCAL_DN_CODE_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_R6C0_LN2_TX_RCAL_DN_CODE_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_TRSV_R6C0_LN2_OVRD_TX_RCAL_COMP_OUT			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_R6C0_LN2_TX_RCAL_COMP_OUT				USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_R6C0_LN2_OVRD_TX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_R6C0_LN2_TX_RCAL_DONE				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_A1B40	(0x1B40)
#define USBDP_TRSV_A1B40_LN2_BIST_EN					USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A1B40_LN2_BIST_DATA_EN				USBDP_COMBO_G2_REG_MSK(6, 1)

#define EXYNOS_USBDP_COM_TRSV_A1B84	(0x1B84)
#define USBDP_TRSV_A1B84_LN2_MON_RX_CDR_AFC_DONE			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A1B84_LN2_MON_RX_CDR_CAL_DONE			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_A1B84_LN2_MON_RX_CDR_FLD_PLL_MODE_DONE		USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_A1B84_LN2_MON_RX_CDR_LOCK_DONE			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_R81E_2078	(0x2078)
#define USBDP_TRSV_R41E_LN2_RX_DFE_ADD_DIS				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_CMN_A2030	(0x2030)
#define USBDP_CMN_A1830_LN3_ANA_TX_JEQ_EN_MSK				USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_A1830_LN3_ANA_TX_JEQ_EN_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_CMN_A1830_LN3_ANA_TX_JEQ_EN_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 4, 4)
#define USBDP_CMN_A1830_LN3_TX_JEQ_EVEN_CTRL_SP_MSK			USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_CMN_A1830_LN3_TX_JEQ_EVEN_CTRL_SP_SET(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_CMN_A1830_LN3_TX_JEQ_EVEN_CTRL_SP_GET(_R)			USBDP_COMBO_G2_REG_GET(_R, 0, 4)

#define EXYNOS_USBDP_COM_TRSV_A205C	(0x205C)
#define USBDP_TRSV_A205C_OVRD_LN3_TX_SER_VREG_EN			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_A205C_LN3_TX_SER_VREG_EN				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_A205C_LN3_ANA_TX_SER_VREG_BYPASS			USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_A205C_OVRD_LN3_TX_SER_VREG_LPF_BYPSS			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_A205C_LN3_TX_SER_VREG_LPF_BYPASS			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_A205C_LN3_ANA_TX_SER_VREG_LADDER_SEL_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_A205C_LN3_ANA_TX_SER_VREG_LADDER_SEL_SET(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_TRSV_A205C_LN3_ANA_TX_SER_VREG_LADDER_SEL_GET(_R)		USBDP_COMBO_G2_REG_GET(_R, 0, 3)

#define EXYNOS_USBDP_COM_TRSV_A20B4	(0x20B4)
#define USBDP_TRSV_A20B4_LN1_RETIMEDLB_EN				USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_A20B4_LN1_BIST_DATA_EN				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_A0A3C	(0x0A3C)
#define EXYNOS_USBDP_COM_TRSV_A1A3C	(0x1A3C)

/* Tune Parameter */
/* Rx squelch detect threshold control */
#define EXYNOS_USBDP_TRSV_26E_09B8	(0x09B8)
#define USBDP_TRSV_26E_LN0_RX_SQHS_TH(_x)				USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_26E_LN0_RX_SQHS_TH_CLR				USBDP_COMBO_G2_REG_CLR(4, 4)
#define USBDP_TRSV_26E_LN0_RX_SQHS_FIL_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_26E_LN0_RX_SQHS_BW_EN(_x)				USBDP_COMBO_G2_REG_SET(_x, 1, 2)
#define USBDP_TRSV_26E_LN0_RX_SQHS_VREF_SEL				USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_066E	(0x19B8)
#define USBDP_TRSV_066E_LN2_RX_SQHS_TH(_x)	USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_066E_LN2_RX_SQHS_TH_CLR	USBDP_COMBO_G2_REG_CLR(4, 4)
#define USBDP_TRSV_066E_LN2_RX_SQHS_FIL_EN		USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_066E_LN2_RX_SQHS_BW_EN(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 2)
#define USBDP_TRSV_066E_LN2_RX_SQHS_VREF_SEL		USBDP_COMBO_G2_REG_MSK(0, 1)
/*LFPS detect threshold control */
#define EXYNOS_USBDP_COM_TRSV_0270	(0x09C0)
#define USBDP_TRSV_0270_LN0_RX_COMP_SKEW_CTRL(_x)	USBDP_COMBO_G2_REG_SET(_x, 6, 2)
#define USBDP_TRSV_0270_LN0_RX_OVRD_LFPS_DET_EN		USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0270_LN0_RX_LFPS_DET_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0270_LN0_RX_LFPS_TH_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 3)
#define USBDP_TRSV_0270_LN0_RX_LFPS_TH_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(1, 3)
#define USBDP_TRSV_0270_LN0_RX_LFPS_I_CTRL		USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_0670	(0x19C0)
#define USBDP_TRSV_0670_LN2_RX_COMP_SKEW_CTRL(_x)	USBDP_COMBO_G2_REG_SET(_x, 6, 2)
#define USBDP_TRSV_0670_LN2_RX_OVRD_LFPS_DET_EN		USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0670_LN2_RX_LFPS_DET_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0670_LN2_RX_LFPS_TH_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 1, 3)
#define USBDP_TRSV_0670_LN2_RX_LFPS_TH_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(1, 3)
#define USBDP_TRSV_0670_LN2_RX_LFPS_I_CTRL		USBDP_COMBO_G2_REG_MSK(0, 1)
/* RX MF EQ Enable */
#define EXYNOS_USBDP_COM_TRSV_0241	(0x0904)
#define USBDP_TRSV_0241_LN0_RX_CTLE_RL_HF_HBR3_MSK	USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_0241_LN0_RX_CTLE_RL_HF_HBR3(_x)	USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_0241_LN0_RX_CTLE_MF_BWD_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0241_LN0_RX_CTLE_OC_DAC_PU		USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0241_LN0_RX_CTLE_OC_DAC_PU_CLR	USBDP_COMBO_G2_REG_CLR(3, 1)
#define USBDP_TRSV_0241_LN0_RX_CTLE_I_MF_FWD_CTRL_MSK	USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_0241_LN0_RX_CTLE_I_MF_FWD_CTRL(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 3)

#define EXYNOS_USBDP_COM_TRSV_0641	(0x1904)
#define USBDP_TRSV_0641_LN2_RX_CTLE_RL_HF_HBR3_MSK	USBDP_COMBO_G2_REG_MSK(5, 3)
#define USBDP_TRSV_0641_LN2_RX_CTLE_RL_HF_HBR3(_x)	USBDP_COMBO_G2_REG_SET(_x, 5, 3)
#define USBDP_TRSV_0641_LN2_RX_CTLE_MF_BWD_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0641_LN2_RX_CTLE_OC_DAC_PU		USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0641_LN2_RX_CTLE_OC_DAC_PU_CLR		USBDP_COMBO_G2_REG_CLR(3, 1)
#define USBDP_TRSV_0641_LN2_RX_CTLE_I_MF_FWD_CTRL_MSK	USBDP_COMBO_G2_REG_MSK(0, 3)
#define USBDP_TRSV_0641_LN2_RX_CTLE_I_MF_FWD_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
/*Rx MF EQ control */
#define EXYNOS_USBDP_COM_TRSV_0311	(0x0C44)
#define USBDP_TRSV_0311_LN0_RX_SSLMS_MF_INIT_RATE_SP_MSK	USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_0311_LN0_RX_SSLMS_MF_INIT_RATE_SP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0311_LN0_RX_SSLMS_MF_INIT_RATE_SP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_0312	(0x0C48)
#define USBDP_TRSV_0312_LN0_RX_SSLMS_MF_INIT_RATE_SSP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0312_LN0_RX_SSLMS_MF_INIT_RATE_SSP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_0711	(0x1C44)
#define USBDP_TRSV_0711_LN2_RX_SSLMS_MF_INIT_RATE_SP_MSK	USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_0711_LN2_RX_SSLMS_MF_INIT_RATE_SP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0711_LN2_RX_SSLMS_MF_INIT_RATE_SP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_0712	(0x1C48)
#define USBDP_TRSV_0712_LN2_RX_SSLMS_MF_INIT_RATE_SSP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0712_LN2_RX_SSLMS_MF_INIT_RATE_SSP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)

/* Rx HF EQ control */
#define EXYNOS_USBDP_COM_TRSV_030B	(0x0C2C)
#define USBDP_TRSV_030B_LN0_RX_SSLMS_HF_INIT_RATE_SP_MSK	USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_030B_LN0_RX_SSLMS_HF_INIT_RATE_SP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_030B_LN0_RX_SSLMS_HF_INIT_RATE_SP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_030C	(0x0C30)
#define USBDP_TRSV_030C_LN0_RX_SSLMS_HF_INIT_RATE_SSP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_030C_LN0_RX_SSLMS_HF_INIT_RATE_SSP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_070B	(0x1C2C)
#define USBDP_TRSV_070B_LN2_RX_SSLMS_HF_INIT_RATE_SP_MSK	USBDP_COMBO_G2_REG_MSK(0, 5)
#define USBDP_TRSV_070B_LN2_RX_SSLMS_HF_INIT_RATE_SP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_070B_LN2_RX_SSLMS_HF_INIT_RATE_SP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)
#define EXYNOS_USBDP_COM_TRSV_070C	(0x1C30)
#define USBDP_TRSV_70C_LN2_RX_SSLMS_HF_INIT_RATE_SSP(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_70C_LN2_RX_SSLMS_HF_INIT_RATE_SSP_CLR	USBDP_COMBO_G2_REG_CLR(0, 5)

/* DFE 1 tap contrl */
#define EXYNOS_USBDP_COM_TRSV_0279	(0x09E4)
#define USBDP_TRSV_0279_LN0_RX_SSLMS_C1_INIT_MSK	USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_0279_LN0_RX_SSLMS_C1_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_0279_LN0_RX_SSLMS_C1_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_0679	(0x19E4)
#define USBDP_TRSV_0679_LN2_RX_SSLMS_C1_INIT_MSK	USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_0679_LN2_RX_SSLMS_C1_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_0679_LN2_RX_SSLMS_C1_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)

/* DFE 2 tap contrl */
#define EXYNOS_USBDP_COM_TRSV_027A	(0x09E8)
#define USBDP_TRSV_027A_LN0_RX_SSLMS_C2_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_027A_LN0_RX_SSLMS_C2_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_067A	(0x19E8)
#define USBDP_TRSV_067A_LN2_RX_SSLMS_C2_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_067A_LN2_RX_SSLMS_C2_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)

/* DFE 3 tap contrl */
#define EXYNOS_USBDP_COM_TRSV_027B	(0x09EC)
#define USBDP_TRSV_027B_LN0_RX_SSLMS_C3_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_027B_LN0_RX_SSLMS_C3_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_067B	(0x19EC)
#define USBDP_TRSV_067B_LN2_RX_SSLMS_C3_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_067B_LN2_RX_SSLMS_C3_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)

/* DFE 4 tap contrl */
#define EXYNOS_USBDP_COM_TRSV_027C	(0x09F0)
#define USBDP_TRSV_027C_LN0_RX_SSLMS_C4_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_027C_LN0_RX_SSLMS_C4_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_067C	(0x19F0)
#define USBDP_TRSV_067C_LN2_RX_SSLMS_C4_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_067C_LN2_RX_SSLMS_C4_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)

/* DFE 5 tap contrl */
#define EXYNOS_USBDP_COM_TRSV_027D	(0x09F4)
#define USBDP_TRSV_027D_LN0_RX_SSLMS_C5_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_027D_LN0_RX_SSLMS_C5_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_067D	(0x19F4)
#define USBDP_TRSV_067D_LN2_RX_SSLMS_C5_INIT(_x)	USBDP_COMBO_G2_REG_SET(_x, 0, 8)
#define USBDP_TRSV_067D_LN2_RX_SSLMS_C5_INIT_CLR	USBDP_COMBO_G2_REG_CLR(0, 8)


/* RX termination */
#define EXYNOS_USBDP_COM_TRSV_02BD	(0x0AF4)
#define USBDP_TRSV_02BD_LN0_RX_OVRD_CAL_RSTN		USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_02BD_LN0_RX_RCAL_RSTN		USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_02BD_LN0_RX_RCAL_OPT_CODE_MSK	USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_02BD_LN0_RX_RCAL_OPT_CODE(_x)	USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_02BD_LN0_RX_RTERM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_02BD_LN0_RX_RTERM_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_02BD_LN0_RX_RTERM_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 4)

#define EXYNOS_USBDP_COM_TRSV_06BD	(0x1AF4)
#define USBDP_TRSV_06BD_LN2_RX_OVRD_CAL_RSTN		USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_06BD_LN2_RX_RCAL_RSTN		USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_06BD_LN2_RX_RCAL_OPT_CODE_MSK	USBDP_COMBO_G2_REG_MSK(4, 2)
#define USBDP_TRSV_06BD_LN2_RX_RCAL_OPT_CODE(_x)	USBDP_COMBO_G2_REG_SET(_x, 4, 2)
#define USBDP_TRSV_06BD_LN2_RX_RTERM_CTRL_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)
#define USBDP_TRSV_06BD_LN2_RX_RTERM_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_06BD_LN2_RX_RTERM_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 4)

/* TX Amplitude */
#define EXYNOS_USBDP_COM_TRSV_0404	(0x1010)
#define USBDP_TRSV_0404_OVRD_LN1_TX_DRV_LVL_CTRL	USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0404_LN1_TX_DRV_LVL_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0404_LN1_TX_DRV_LVL_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 5)

#define EXYNOS_USBDP_COM_TRSV_0804	(0x2010)
#define USBDP_TRSV_0804_OVRD_LN3_TX_DRV_LVL_CTRL	USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0804_LN3_TX_DRV_LVL_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 5)
#define USBDP_TRSV_0804_LN3_TX_DRV_LVL_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 5)
/* TX De-emphasis */
#define EXYNOS_USBDP_COM_TRSV_0405	(0x1014)
#define USBDP_TRSV_0405_OVRD_LN1_TX_DRV_POST_LVL_CTRL		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0405_LN1_TX_DRV_POST_LVL_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_0405_LN1_TX_DRV_POST_LVL_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 4)

#define EXYNOS_USBDP_COM_TRSV_0805	(0x2014)
#define USBDP_TRSV_0805_OVRD_LN3_TX_DRV_POST_LVL_CTRL		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0805_LN3_TX_DRV_LVL_POST_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_0805_LN3_TX_DRV_LVL_POST_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 4)

/* TX Pre-Shoot */
#define EXYNOS_USBDP_COM_TRSV_0406	(0x1018)
#define USBDP_TRSV_0406_OVRD_LN1_TX_DRV_PRE_LVL_CTRL		USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0406_LN1_TX_DRV_PRE_LVL_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 4)
#define USBDP_TRSV_0406_LN1_TX_DRV_PRE_LVL_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(2, 4)
#define USBDP_TRSV_0406_LN1_TX_OVRD_DRV_IDRV_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0406_LN1_TX_DRV_IDRV_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_0806	(0x2018)
#define USBDP_TRSV_0806_OVRD_LN3_TX_DRV_PRE_LVL_CTRL		USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0806_LN3_TX_DRV_PRE_LVL_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 4)
#define USBDP_TRSV_0806_LN3_TX_DRV_PRE_LVL_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(2, 4)
#define USBDP_TRSV_0806_LN3_TX_OVRD_DRV_IDRV_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0806_LN3_TX_DRV_IDRV_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

/* TX IDRV UP */
#if !defined(CONFIG_SOC_EXYNOS9820_EVT0)
	#define EXYNOS_USBDP_COM_TRSV_0407	(0x101C)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IUP_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IUP_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(5, 3)

	#define EXYNOS_USBDP_COM_TRSV_0807	(0x201C)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IUP_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IUP_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(5, 3)
#else
	#define EXYNOS_USBDP_COM_TRSV_0407	(0x101C)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(5, 3)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IUP_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_IUP_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(2, 3)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_VREF_SEL		USBDP_COMBO_G2_REG_MSK(1, 1)
	#define USBDP_TRSV_0407_LN1_TX_DRV_IDRV_ACCDRV_EN		USBDP_COMBO_G2_REG_MSK(0, 1)

	#define EXYNOS_USBDP_COM_TRSV_0807	(0x201C)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 5, 3)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(5, 3)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IUP_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 3)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_IUP_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(2, 3)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_VREF_SEL		USBDP_COMBO_G2_REG_MSK(1, 1)
	#define USBDP_TRSV_0807_LN3_TX_DRV_IDRV_ACCDRV_EN		USBDP_COMBO_G2_REG_MSK(0, 1)
#endif
/* TX IDRV DN */
#define EXYNOS_USBDP_COM_CMN_041C	(0x041C)
#define USBDP_CMN_041C_LN0_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 3)
#define USBDP_CMN_041C_LN0_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(4, 3)
#define USBDP_CMN_041C_LN1_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_CMN_041C_LN1_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 3)

#define EXYNOS_USBDP_COM_CMN_0420	(0x0420)
#define USBDP_CMN_0420_LN2_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 4, 3)
#define USBDP_CMN_0420_LN2_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(4, 3)
#define USBDP_CMN_0420_LN3_TX_DRV_IDRV_IDN_CTRL(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 3)
#define USBDP_CMN_0420_LN3_TX_DRV_IDRV_IDN_CTRL_CLR		USBDP_COMBO_G2_REG_CLR(0, 3)

/* TX UP/DN termination */
#define EXYNOS_USBDP_COM_TRSV_0420	(0x1080)
#define USBDP_TRSV_0420_LN1_TX_RCAL_UP_CODE(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_0420_LN1_TX_RCAL_UP_CODE_CLR			USBDP_COMBO_G2_REG_CLR(4, 4)
#define USBDP_TRSV_0420_LN1_TX_RCAL_DN_CODE(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_0420_LN1_TX_RCAL_DN_CODE_CLR			USBDP_COMBO_G2_REG_CLR(0, 4)

#define EXYNOS_USBDP_COM_TRSV_0820	(0x2080)
#define USBDP_TRSV_0820_LN3_TX_RCAL_UP_CODE(_x)			USBDP_COMBO_G2_REG_SET(_x, 4, 4)
#define USBDP_TRSV_0820_LN3_TX_RCAL_UP_CODE_CLR			USBDP_COMBO_G2_REG_CLR(4, 4)
#define USBDP_TRSV_0820_LN3_TX_RCAL_DN_CODE(_x)			USBDP_COMBO_G2_REG_SET(_x, 0, 4)
#define USBDP_TRSV_0820_LN3_TX_RCAL_DN_CODE_CLR			USBDP_COMBO_G2_REG_CLR(0, 4)

/* tune control */
/* RX tune */
#define EXYNOS_USBDP_COM_TRSV_028C	(0x0A30)
#define USBDP_TRSV_028C_LN0_RX_SSLMS_ADAP_COEF_SEL		USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_028C_LN0_RX_SSLMS_ADAP_COEF_SEL_CLR		USBDP_COMBO_G2_REG_CLR(0, 8)
#define EXYNOS_USBDP_COM_TRSV_068C	(0x1A30)
#define USBDP_TRSV_068C_LN2_RX_SSLMS_ADAP_COEF_SEL		USBDP_COMBO_G2_REG_MSK(0, 8)
#define USBDP_TRSV_068C_LN2_RX_SSLMS_ADAP_COEF_SEL_CLR		USBDP_COMBO_G2_REG_CLR(0, 8)

/* TX up/dn term tune */
#define EXYNOS_USBDP_COM_TRSV_041F	(0x107C)
#define USBDP_TRSV_041F_LN1_TX_RCAL_UP_OPT_CODE(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 2)
#define USBDP_TRSV_041F_LN1_TX_RCAL_UP_OPT_CODE_CLR		USBDP_COMBO_G2_REG_CLR(2, 2)
#define USBDP_TRSV_041F_LN1_TX_RCAL_DN_OPT_CODE(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_041F_LN1_TX_RCAL_DN_OPT_CODE_CLR		USBDP_COMBO_G2_REG_CLR(0, 2)
#define EXYNOS_USBDP_COM_TRSV_081F	(0x207C)
#define USBDP_TRSV_081F_LN3_TX_RCAL_UP_OPT_CODE(_x)		USBDP_COMBO_G2_REG_SET(_x, 2, 2)
#define USBDP_TRSV_081F_LN3_TX_RCAL_UP_OPT_CODE_CLR		USBDP_COMBO_G2_REG_CLR(2, 2)
#define USBDP_TRSV_081F_LN3_TX_RCAL_DN_OPT_CODE(_x)		USBDP_COMBO_G2_REG_SET(_x, 0, 2)
#define USBDP_TRSV_081F_LN3_TX_RCAL_DN_OPT_CODE_CLR		USBDP_COMBO_G2_REG_CLR(0, 2)


/* DP unused TX1 lane lfps overide */
#define EXYNOS_USBDP_COM_TRSV_0400	(0x1000)
#define USBDP_TRSV_0400_OVRD_LN1_TX_DRV_EN			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_0400_LN1_TX_DRV_EN				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0400_OVRD_LN1_TX_DRV_BEACON_LFPS_OUT_EN	USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0400_LN1_TX_DRV_BEACON_LFPS_OUT_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_EN	USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0400_LN1_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL	USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_0400_OVRD_LN1_TX_DRV_CM_KEEPER_EN		USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0400_LN1_TX_DRV_CM_KEEPER_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

/* DP unused TX3 lane lfps overide */
#define EXYNOS_USBDP_COM_TRSV_0800	(0x2000)
#define USBDP_TRSV_0800_OVRD_LN3_TX_DRV_EN			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_TRSV_0800_LN3_TX_DRV_EN				USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0800_OVRD_LN3_TX_DRV_BEACON_LFPS_OUT_EN	USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0800_LN3_TX_DRV_BEACON_LFPS_OUT_EN		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_EN	USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0800_LN3_ANA_TX_DRV_BEACON_LFPS_SYNC_SEL	USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_0800_OVRD_LN3_TX_DRV_CM_KEEPER_EN		USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0800_LN3_TX_DRV_CM_KEEPER_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_COM_TRSV_02BC	(0x0AF0)
#define USBDP_TRSV_02BC_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 2, 3)
#define USBDP_TRSV_02BC_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_CLR		USBDP_COMBO_G2_REG_CLR(2, 3)
#define USBDP_TRSV_02BC_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_MSK		USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_TRSV_02BC_LN0_TG_RX_SIGVAL_LPF_DELAY_TIME_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 2, 3)
#define USBDP_TRSV_02BC_LN0_TB_RX_SIGVAL_LPF_BYPASS(_val)		USBDP_COMBO_G2_REG_SET(_val, 5, 2)

#define EXYNOS_USBDP_COM_TRSV_06BC	(0x1AF0)
#define USBDP_TRSV_06BC_LN2_TG_RX_SIGVAL_LPF_DELAY_TIME_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 2, 3)
#define USBDP_TRSV_06BC_LN2_TG_RX_SIGVAL_LPF_DELAY_TIME_CLR		USBDP_COMBO_G2_REG_CLR(2, 3)
#define USBDP_TRSV_06BC_LN2_TG_RX_SIGVAL_LPF_DELAY_TIME_MSK		USBDP_COMBO_G2_REG_MSK(2, 3)
#define USBDP_TRSV_06BC_LN2_TG_RX_SIGVAL_LPF_DELAY_TIME_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 2, 3)

/* long channel rx data loss enhance */
#define EXYNOS_USBDP_TRSV_08DC	(0x08DC)
#define USBDP_TRSV_0237_OVRD_LN0_RX_CTLE_EN			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0237_LN0_RX_CTLE_EN				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0237_OVRD_LN0_RX_CTLE_OC_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0237_LN0_RX_CTLE_OC_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0237_OVRD_LN0_RX_CTLE_MF_FWD_EN		USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_0237_LN0_RX_CTLE_MF_FWD_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0237_LN0_ANA_RX_CTLE_HF_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_18DC	(0x18DC)
#define USBDP_TRSV_0637_OVRD_LN2_RX_CTLE_EN			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_TRSV_0637_LN2_RX_CTLE_EN				USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_TRSV_0637_OVRD_LN2_RX_CTLE_OC_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_0637_LN2_RX_CTLE_OC_EN			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_0637_OVRD_LN2_RX_CTLE_MF_FWD_EN		USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_0637_LN2_RX_CTLE_MF_FWD_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_0637_LN2_ANA_RX_CTLE_HF_EN			USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_09AC	(0x09AC)
#define USBDP_TRSV_09AC_LN0_ANA_RX_SQ_VREF_820M_SEL_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 5, 2)
#define USBDP_TRSV_09AC_LN0_ANA_RX_SQ_VREF_820M_SEL_CLR		USBDP_COMBO_G2_REG_CLR(5, 2)
#define USBDP_TRSV_09AC_OVRD_LN0_RX_SQHS_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_09AC_LN0_RX_SQHS_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_09AC_OVRD_LN0_RX_SQHS_DIFN_OC_EN		USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_09AC_LN0_RX_SQHS_DIFN_OC_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_09AC_LN0_ANA_RX_SQHS_DIFN_OC_CODE_SIGN	USBDP_COMBO_G2_REG_MSK(0, 1)

#define EXYNOS_USBDP_TRSV_19AC	(0x19AC)
#define USBDP_TRSV_066B_LN2_ANA_RX_SQ_VREF_820M_SEL(_val)	USBDP_COMBO_G2_REG_SET(_val, 5, 2)
#define USBDP_TRSV_066B_LN2_ANA_RX_SQ_VREF_820M_SEL_CLR		USBDP_COMBO_G2_REG_CLR(5, 2)
#define USBDP_TRSV_066B_OVRD_LN2_RX_SQHS_EN			USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_TRSV_066B_LN2_RX_SQHS_EN				USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_TRSV_066B_OVRD_LN2_RX_SQHS_DIFN_OC_EN		USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_TRSV_066B_LN2_RX_SQHS_DIFN_OC_EN			USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_TRSV_066B_LN2_ANA_RX_SQHS_DIFN_OC_CODE_SIGN	USBDP_COMBO_G2_REG_MSK(0, 1)

/* PCS Register */
#define USBDP_GEN2_PCSREG_EBUF_PARAM			0x0304
#define USBDPG2_PCS_NUM_INIT_BUFFERING_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 16, 6)
#define USBDPG2_PCS_NUM_INIT_BUFFERING_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 16, 6)
#define USBDPG2_PCS_NUM_INIT_BUFFERING_MSK		USBDP_COMBO_G2_REG_MSK(16, 6)
#define USBDPG2_PCS_SKP_INSERT_TH_SET(_val)		USBDP_COMBO_G2_REG_SET(_val, 8, 6)
#define USBDPG2_PCS_SKP_INSERT_TH_GET(_reg)		USBDP_COMBO_G2_REG_GET(_reg, 8, 6)
#define USBDPG2_PCS_SKP_INSERT_TH_MSK			USBDP_COMBO_G2_REG_MSK(8, 6)
#define USBDPG2_PCS_SKP_REMOVE_TH_SET(_val)		USBDP_COMBO_G2_REG_SET(_val, 0, 6)
#define USBDPG2_PCS_SKP_REMOVE_TH_GET(_reg)		USBDP_COMBO_G2_REG_GET(_reg, 0, 6)
#define USBDPG2_PCS_SKP_REMOVE_TH_MSK			USBDP_COMBO_G2_REG_MSK(0, 6)

#define USBDP_GEN2_PCSREG_BACK_END_MODE_VEC		0x030C
#define USBDPG2_PCS_DISABLE_DATA_MASK_MSK		USBDP_COMBO_G2_REG_MSK(0, 1)

#define USBDP_GEN2_PCSREG_EBUF_DRAINER_PARAM		0x0318
#define USBDP_GEN2_PCSREG_EN_MASK_TSEQ			USBDP_COMBO_G2_REG_MSK(17, 1)
#define USBDP_GEN2_PCSREG_EN_REMOVE_TSEQ		USBDP_COMBO_G2_REG_MSK(16, 1)

#define USBDP_GEN2_PCSREG_OUT_VEC_0			0x0144
#define USBDP_GEN2_PCSREG_OUT_VEC_1			0x0148
#define USBDP_GEN2_PCSREG_OUT_VEC_2			0x014C
#define USBDP_GEN2_PCSREG_OUT_VEC_3			0x0150


/* EVT1 added - 20180706 */
#define EXYNOS_USBDP_TRSV_0994					0x0994
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 3, 3)
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 3, 3)
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SP_MSK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SSP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 3)
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SSP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 3)
#define USBDP_TRSV_0265_LN0_RX_DFE_VGA_RL_CTRL_SSP_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)

#define EXYNOS_USBDP_TRSV_1994					0x1994
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 3, 3)
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 3, 3)
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SP_MSK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SSP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 3)
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SSP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 3)
#define USBDP_TRSV_0665_LN2_RX_DFE_VGA_RL_CTRL_SSP_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)

#define EXYNOS_USBDP_TRSV_0898					0x0898
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 4, 4)
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 4, 4)
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SP_MSK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SSP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 4)
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SSP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 4)
#define USBDP_TRSV_0226_LN0_RX_CDR_MDIV_SEL_PLL_SSP_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)

#define EXYNOS_USBDP_TRSV_1898					0x1898
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 4, 4)
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 4, 4)
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SP_MSK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SSP_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 4)
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SSP_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 4)
#define USBDP_TRSV_0626_LN2_RX_CDR_MDIV_SEL_PLL_SSP_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)

#define EXYNOS_USBDP_CMN_0060					0x0060
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_COARSE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 3, 3)
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_COARSE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 3, 3)
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_COARSE_MSK		USBDP_COMBO_G2_REG_MSK(3, 3)
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_FINE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 3)
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_FINE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 3)
#define USBDP_CMN_0018_LCPLL_ANA_CPI_CTRL_FINE_MSK		USBDP_COMBO_G2_REG_MSK(0, 3)

#define EXYNOS_USBDP_CMN_0064					0x0064
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_COARSE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 4, 4)
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_COARSE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 4, 4)
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_COARSE_MSK		USBDP_COMBO_G2_REG_MSK(4, 4)
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_FINE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 4)
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_FINE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 4)
#define USBDP_CMN_0019_LCPLL_ANA_CPP_CTRL_FINE_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)

#define EXYNOS_USBDP_CMN_0070					0x0070
#define USBDP_CMN_001C_LCPLL_ANA_LPF_C_SEL_FINE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 4, 3)
#define USBDP_CMN_001C_LCPLL_ANA_LPF_C_SEL_FINE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 4, 3)
#define USBDP_CMN_001C_LCPLL_ANA_LPF_C_SEL_FINE_MSK		USBDP_COMBO_G2_REG_MSK(4, 3)
#define USBDP_CMN_001C_LCPLL_ANA_LPF_R_SEL_COARSE_SET(_val)	USBDP_COMBO_G2_REG_SET(_val, 0, 4)
#define USBDP_CMN_001C_LCPLL_ANA_LPF_R_SEL_COARSE_GET(_reg)	USBDP_COMBO_G2_REG_GET(_reg, 0, 4)
#define USBDP_CMN_001C_LCPLL_ANA_LPF_R_SEL_COARSE_MSK		USBDP_COMBO_G2_REG_MSK(0, 4)

#define EXYNOS_USBDP_TRSV_0B04					0x0B04
#define USBDP_TRSV_02C1_LN0_MISC_TX_CLK_SRC			USBDP_COMBO_G2_REG_MSK(2, 1)

#define EXYNOS_USBDP_TRSV_0878					0x0878
#define EXYNOS_USBDP_TRSV_1878					0x1878
/* EVT1 added - 20180706 */

#define USBDP_GEN2_PCSREG_DYN_CON_PWR_DWN		USBDP_COMBO_G2_REG_MSK(19, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_PWR_DWN		USBDP_COMBO_G2_REG_MSK(18, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_RX_CTLE		USBDP_COMBO_G2_REG_MSK(17, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_RX_CTLE		USBDP_COMBO_G2_REG_MSK(16, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_PMA_TX_KEEPER		USBDP_COMBO_G2_REG_MSK(15, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_PMA_TX_KEEPER		USBDP_COMBO_G2_REG_MSK(14, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_TX_DRVR		USBDP_COMBO_G2_REG_MSK(13, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_TX_DRVR		USBDP_COMBO_G2_REG_MSK(12, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_TX_SER		USBDP_COMBO_G2_REG_MSK(11, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_TX_SER		USBDP_COMBO_G2_REG_MSK(10, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_DESERIAL		USBDP_COMBO_G2_REG_MSK(9, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_DESERIAL		USBDP_COMBO_G2_REG_MSK(8, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_CDR			USBDP_COMBO_G2_REG_MSK(7, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_CDR			USBDP_COMBO_G2_REG_MSK(6, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_RX_SQHS		USBDP_COMBO_G2_REG_MSK(5, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_RX_SQHS		USBDP_COMBO_G2_REG_MSK(4, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_PLL			USBDP_COMBO_G2_REG_MSK(3, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_PLL			USBDP_COMBO_G2_REG_MSK(2, 1)
#define USBDP_GEN2_PCSREG_DYN_CON_BGR_BIAS		USBDP_COMBO_G2_REG_MSK(1, 1)
#define USBDP_GEN2_PCSREG_SEL_OUT_BGR_BIAS		USBDP_COMBO_G2_REG_MSK(0, 1)

#endif /* _PHY_EXYNOS_USBDP_G2_REG_H_ */