diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 40d20b4..9ce21f6 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -307,8 +307,8 @@
 	GET_PDA(p0, r0);
 	r0 = [p0 + PDA_IRQFLAGS];
 #else
-	p0.h = _irq_flags;
-	p0.l = _irq_flags;
+	p0.h = _bfin_irq_flags;
+	p0.l = _bfin_irq_flags;
 	r0 = [p0];
 #endif
 	sti r0;
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index e43c205..21e25f7 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -49,16 +49,16 @@
 /* Forward decl needed due to cdef inter dependencies */
 static inline uint32_t __pure bfin_dspid(void);
 # define blackfin_core_id() (bfin_dspid() & 0xff)
-# define irq_flags cpu_pda[blackfin_core_id()].imask
+# define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
 #else
-extern unsigned long irq_flags;
+extern unsigned long bfin_irq_flags;
 #endif
 
 #define local_irq_enable() \
 	__asm__ __volatile__( \
 		"sti %0;" \
 		: \
-		: "d" (irq_flags) \
+		: "d" (bfin_irq_flags) \
 	)
 
 #define idle_with_irq_disabled() \
@@ -68,7 +68,7 @@
 		"sti %0;" \
 		"idle;" \
 		: \
-		: "d" (irq_flags) \
+		: "d" (bfin_irq_flags) \
 	)
 
 #ifdef CONFIG_DEBUG_HWERR
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 5531f49..e22c0a5 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -922,8 +922,8 @@
 	GET_PDA(p0, r0); 	/* Fetch current PDA (can't migrate to other CPU here) */
 	r0 = [p0 + PDA_IRQFLAGS];
 #else
-	p0.l = _irq_flags;
-	p0.h = _irq_flags;
+	p0.l = _bfin_irq_flags;
+	p0.h = _bfin_irq_flags;
 	r0 = [p0];
 #endif
 	sti r0;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 2efddce..5a7c1c1 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -64,8 +64,8 @@
  * it would live otherwise).  The 0x1f magic represents the IRQs we
  * cannot actually mask out in hardware.
  */
-unsigned long irq_flags = 0x1f;
-EXPORT_SYMBOL(irq_flags);
+unsigned long bfin_irq_flags = 0x1f;
+EXPORT_SYMBOL(bfin_irq_flags);
 #endif
 
 /* The number of spurious interrupts */
@@ -134,21 +134,21 @@
 
 static void bfin_core_mask_irq(unsigned int irq)
 {
-	irq_flags &= ~(1 << irq);
+	bfin_irq_flags &= ~(1 << irq);
 	if (!irqs_disabled())
 		local_irq_enable();
 }
 
 static void bfin_core_unmask_irq(unsigned int irq)
 {
-	irq_flags |= 1 << irq;
+	bfin_irq_flags |= 1 << irq;
 	/*
 	 * If interrupts are enabled, IMASK must contain the same value
-	 * as irq_flags.  Make sure that invariant holds.  If interrupts
+	 * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 	 * are currently disabled we need not do anything; one of the
 	 * callers will take care of setting IMASK to the proper value
 	 * when reenabling interrupts.
-	 * local_irq_enable just does "STI irq_flags", so it's exactly
+	 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 	 * what we need.
 	 */
 	if (!irqs_disabled())
@@ -1048,7 +1048,7 @@
 	CSYNC();
 
 	printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
-	/* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
+	/* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
 	 * local_irq_enable()
 	 */
 	program_IAR();
@@ -1056,7 +1056,7 @@
 	search_IAR();
 
 	/* Enable interrupts IVG7-15 */
-	irq_flags |= IMASK_IVG15 |
+	bfin_irq_flags |= IMASK_IVG15 |
 	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
 
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 7aeeced..66c47a7 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -365,7 +365,7 @@
 
 	/* Enable interrupt levels IVG7-15. IARs have been already
 	 * programmed by the boot CPU.  */
-	irq_flags |= IMASK_IVG15 |
+	bfin_irq_flags |= IMASK_IVG15 |
 	    IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
 	    IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;