commit 2cea752f683af1be58ee8f25717c0a8118e0ac5b
author R.Marek@sh.cvut.cz <R.Marek@sh.cvut.cz> Tue Sep 27 21:54:51 2005 +0000
committer Greg Kroah-Hartman <gregkh@suse.de> Fri Oct 28 15:36:58 2005 -0700
tree a0d40566377824eb6cfe5faac802140392dcee28
parent 20731945ae743034353a88c307920d1f16cf8ac8

[PATCH] PCI: ICH6 ACPI and GPIO quirk

This patch just adds ACPI and GPIO regions to its LPC bridge, similar
way as ICH4 did. I would like to thank Michal Mleczko for testing.

Signed-off-by: Rudolf Marek <r.marek@sh.cvut.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

 drivers/pci/quirks.c |   12 ++++++++++++
 1 file changed, 12 insertions(+)

drivers/pci/quirks.c

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 7992bc8..0663428 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -414,6 +414,18 @@
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi );
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi );
 
+static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
+{
+	u32 region;
+
+	pci_read_config_dword(dev, 0x40, &region);
+	quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
+
+	pci_read_config_dword(dev, 0x48, &region);
+	quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
+
 /*
  * VIA ACPI: One IO region pointed to by longword at
  *	0x48 or 0x20 (256 bytes of ACPI registers)