tree 547dd387e73f0d74eb53cdc7c493f6fc8126aaf9
parent a3f457d9636b3f5ae4fc6502cb0c95f60f5e342b
author Xing Zheng <zhengxing@rock-chips.com> 1470122398 +0800
committer Heiko Stuebner <heiko@sntech.de> 1470989092 +0200

clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>