1. e04ed38 sparc64: Fix Niagara2 perf event handling. by David S. Miller · 15 years ago
  2. de23cf3 sparc64: Fix niagara2 perf IRQ bits. by David S. Miller · 15 years ago
  3. d175138 sparc64: Cache per-cpu %pcr register value in perf code. by David S. Miller · 15 years ago
  4. 6e80425 sparc64: Fix comment typo in perf_event.c by David S. Miller · 15 years ago
  5. d29862f sparc64: Minor coding style fixups in perf code. by David S. Miller · 15 years ago
  6. a72a8a5 sparc64: Add a basic conflict engine in preparation for multi-counter support. by David S. Miller · 15 years ago
  7. 01552f7 sparc64: Add initial perf event conflict resolution and checks. by David S. Miller · 15 years ago
  8. 7eebda6 sparc: Niagara1 perf event support. by David S. Miller · 15 years ago
  9. d0b8648 sparc: Add Niagara2 HW cache event support. by David S. Miller · 15 years ago
  10. 28e8f9b sparc: Support all ultra3 and ultra4 derivatives. by David S. Miller · 15 years ago
  11. 2ce4da2 sparc: Support HW cache events. by David S. Miller · 15 years ago
  12. cdd6c48 perf: Do the big rename: Performance Counters -> Performance Events by Ingo Molnar · 15 years ago[Renamed (68%) from arch/sparc/kernel/perf_counter.c]
  13. cd74c86 perf_counter, powerpc, sparc: Fix compilation after perf_counter_overflow() change by Paul Mackerras · 15 years ago
  14. b73d884 sparc64: Initial niagara2 perf counter support. by David S. Miller · 15 years ago
  15. 660d137 sparc64: Perf counter 'nop' event is not constant. by David S. Miller · 15 years ago
  16. 496c07e sparc64: Provide a way to specify a perf counter overflow IRQ enable bit. by David S. Miller · 15 years ago
  17. 91b9286 sparc64: Provide hypervisor tracing bit support for perf counters. by David S. Miller · 15 years ago
  18. 59abbd1 sparc64: Initial hw perf counter support. by David S. Miller · 15 years ago