David S. Miller | 9fd8b64 | 2007-03-08 21:55:49 -0800 | [diff] [blame] | 1 | /* pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * |
David S. Miller | 9fd8b64 | 2007-03-08 21:55:49 -0800 | [diff] [blame] | 3 | * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
| 5 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) |
| 6 | */ |
| 7 | |
| 8 | #include <linux/kernel.h> |
| 9 | #include <linux/types.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/init.h> |
Paul Gortmaker | 7b64db6 | 2011-07-18 15:57:46 -0400 | [diff] [blame] | 12 | #include <linux/export.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/slab.h> |
| 14 | #include <linux/interrupt.h> |
Stephen Rothwell | 764f257 | 2008-08-07 15:33:36 -0700 | [diff] [blame] | 15 | #include <linux/of_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <asm/iommu.h> |
| 18 | #include <asm/irq.h> |
| 19 | #include <asm/starfire.h> |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 20 | #include <asm/prom.h> |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 21 | #include <asm/upa.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | |
| 23 | #include "pci_impl.h" |
| 24 | #include "iommu_common.h" |
David S. Miller | a21cff3 | 2008-09-10 03:07:03 -0700 | [diff] [blame] | 25 | #include "psycho_common.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 27 | #define DRIVER_NAME "psycho" |
| 28 | #define PFX DRIVER_NAME ": " |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | /* Misc. PSYCHO PCI controller register offsets and definitions. */ |
| 31 | #define PSYCHO_CONTROL 0x0010UL |
| 32 | #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ |
| 33 | #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ |
| 34 | #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ |
| 35 | #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ |
| 36 | #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ |
| 37 | #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ |
| 38 | #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ |
| 39 | #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ |
| 40 | #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ |
| 41 | #define PSYCHO_PCIA_CTRL 0x2000UL |
| 42 | #define PSYCHO_PCIB_CTRL 0x4000UL |
| 43 | #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ |
| 44 | #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ |
| 45 | #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ |
| 46 | #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ |
| 47 | #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ |
| 48 | #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ |
| 49 | #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ |
| 50 | #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ |
| 51 | #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ |
| 52 | #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
| 53 | #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ |
| 54 | #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ |
| 55 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | /* PSYCHO error handling support. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | |
| 58 | /* Helper function of IOMMU error checking, which checks out |
| 59 | * the state of the streaming buffers. The IOMMU lock is |
| 60 | * held when this is called. |
| 61 | * |
| 62 | * For the PCI error case we know which PBM (and thus which |
| 63 | * streaming buffer) caused the error, but for the uncorrectable |
| 64 | * error case we do not. So we always check both streaming caches. |
| 65 | */ |
| 66 | #define PSYCHO_STRBUF_CONTROL_A 0x2800UL |
| 67 | #define PSYCHO_STRBUF_CONTROL_B 0x4800UL |
| 68 | #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ |
| 69 | #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ |
| 70 | #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ |
| 71 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
| 72 | #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ |
| 73 | #define PSYCHO_STRBUF_FLUSH_A 0x2808UL |
| 74 | #define PSYCHO_STRBUF_FLUSH_B 0x4808UL |
| 75 | #define PSYCHO_STRBUF_FSYNC_A 0x2810UL |
| 76 | #define PSYCHO_STRBUF_FSYNC_B 0x4810UL |
| 77 | #define PSYCHO_STC_DATA_A 0xb000UL |
| 78 | #define PSYCHO_STC_DATA_B 0xc000UL |
| 79 | #define PSYCHO_STC_ERR_A 0xb400UL |
| 80 | #define PSYCHO_STC_ERR_B 0xc400UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | #define PSYCHO_STC_TAG_A 0xb800UL |
| 82 | #define PSYCHO_STC_TAG_B 0xc800UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | #define PSYCHO_STC_LINE_A 0xb900UL |
| 84 | #define PSYCHO_STC_LINE_B 0xc900UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | /* When an Uncorrectable Error or a PCI Error happens, we |
| 87 | * interrogate the IOMMU state to see if it is the cause. |
| 88 | */ |
| 89 | #define PSYCHO_IOMMU_CONTROL 0x0200UL |
| 90 | #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ |
| 91 | #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ |
| 92 | #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ |
| 93 | #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ |
| 94 | #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ |
| 95 | #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
| 96 | #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ |
| 97 | #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ |
| 98 | #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ |
| 99 | #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ |
| 100 | #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ |
| 101 | #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ |
| 102 | #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ |
| 103 | #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ |
| 104 | #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ |
| 105 | #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ |
| 106 | #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ |
| 107 | #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
| 108 | #define PSYCHO_IOMMU_TSBBASE 0x0208UL |
| 109 | #define PSYCHO_IOMMU_FLUSH 0x0210UL |
| 110 | #define PSYCHO_IOMMU_TAG 0xa580UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | #define PSYCHO_IOMMU_DATA 0xa600UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | |
| 113 | /* Uncorrectable Errors. Cause of the error and the address are |
| 114 | * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors |
| 115 | * relating to UPA interface transactions. |
| 116 | */ |
| 117 | #define PSYCHO_UE_AFSR 0x0030UL |
| 118 | #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 119 | #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 120 | #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 121 | #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 122 | #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 123 | #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 124 | #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| 125 | #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 126 | #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ |
| 127 | #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 128 | #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 129 | #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 130 | #define PSYCHO_UE_AFAR 0x0038UL |
| 131 | |
Al Viro | 6d24c8d | 2006-10-08 08:23:28 -0400 | [diff] [blame] | 132 | static irqreturn_t psycho_ue_intr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | { |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 134 | struct pci_pbm_info *pbm = dev_id; |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 135 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR; |
| 136 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | unsigned long afsr, afar, error_bits; |
| 138 | int reported; |
| 139 | |
| 140 | /* Latch uncorrectable error status. */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 141 | afar = upa_readq(afar_reg); |
| 142 | afsr = upa_readq(afsr_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | |
| 144 | /* Clear the primary/secondary error status bits. */ |
| 145 | error_bits = afsr & |
| 146 | (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | |
| 147 | PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); |
| 148 | if (!error_bits) |
| 149 | return IRQ_NONE; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 150 | upa_writeq(error_bits, afsr_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | |
| 152 | /* Log the error. */ |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 153 | printk("%s: Uncorrectable Error, primary error type[%s]\n", |
| 154 | pbm->name, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | (((error_bits & PSYCHO_UEAFSR_PPIO) ? |
| 156 | "PIO" : |
| 157 | ((error_bits & PSYCHO_UEAFSR_PDRD) ? |
| 158 | "DMA Read" : |
| 159 | ((error_bits & PSYCHO_UEAFSR_PDWR) ? |
| 160 | "DMA Write" : "???"))))); |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 161 | printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
| 162 | pbm->name, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
| 164 | (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, |
| 165 | (afsr & PSYCHO_UEAFSR_MID) >> 24UL, |
| 166 | ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 167 | printk("%s: UE AFAR [%016lx]\n", pbm->name, afar); |
| 168 | printk("%s: UE Secondary errors [", pbm->name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | reported = 0; |
| 170 | if (afsr & PSYCHO_UEAFSR_SPIO) { |
| 171 | reported++; |
| 172 | printk("(PIO)"); |
| 173 | } |
| 174 | if (afsr & PSYCHO_UEAFSR_SDRD) { |
| 175 | reported++; |
| 176 | printk("(DMA Read)"); |
| 177 | } |
| 178 | if (afsr & PSYCHO_UEAFSR_SDWR) { |
| 179 | reported++; |
| 180 | printk("(DMA Write)"); |
| 181 | } |
| 182 | if (!reported) |
| 183 | printk("(none)"); |
| 184 | printk("]\n"); |
| 185 | |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 186 | /* Interrogate both IOMMUs for error status. */ |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 187 | psycho_check_iommu_error(pbm, afsr, afar, UE_ERR); |
| 188 | if (pbm->sibling) |
| 189 | psycho_check_iommu_error(pbm->sibling, afsr, afar, UE_ERR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | |
| 191 | return IRQ_HANDLED; |
| 192 | } |
| 193 | |
| 194 | /* Correctable Errors. */ |
| 195 | #define PSYCHO_CE_AFSR 0x0040UL |
| 196 | #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 197 | #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 198 | #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 199 | #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 200 | #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 201 | #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 202 | #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
| 203 | #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
| 204 | #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 205 | #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ |
| 206 | #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 207 | #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 208 | #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 209 | #define PSYCHO_CE_AFAR 0x0040UL |
| 210 | |
Al Viro | 6d24c8d | 2006-10-08 08:23:28 -0400 | [diff] [blame] | 211 | static irqreturn_t psycho_ce_intr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | { |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 213 | struct pci_pbm_info *pbm = dev_id; |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 214 | unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR; |
| 215 | unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | unsigned long afsr, afar, error_bits; |
| 217 | int reported; |
| 218 | |
| 219 | /* Latch error status. */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 220 | afar = upa_readq(afar_reg); |
| 221 | afsr = upa_readq(afsr_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | |
| 223 | /* Clear primary/secondary error status bits. */ |
| 224 | error_bits = afsr & |
| 225 | (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | |
| 226 | PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); |
| 227 | if (!error_bits) |
| 228 | return IRQ_NONE; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 229 | upa_writeq(error_bits, afsr_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | |
| 231 | /* Log the error. */ |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 232 | printk("%s: Correctable Error, primary error type[%s]\n", |
| 233 | pbm->name, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | (((error_bits & PSYCHO_CEAFSR_PPIO) ? |
| 235 | "PIO" : |
| 236 | ((error_bits & PSYCHO_CEAFSR_PDRD) ? |
| 237 | "DMA Read" : |
| 238 | ((error_bits & PSYCHO_CEAFSR_PDWR) ? |
| 239 | "DMA Write" : "???"))))); |
| 240 | |
| 241 | /* XXX Use syndrome and afar to print out module string just like |
| 242 | * XXX UDB CE trap handler does... -DaveM |
| 243 | */ |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 244 | printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | "UPA_MID[%02lx] was_block(%d)\n", |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 246 | pbm->name, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
| 248 | (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, |
| 249 | (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, |
| 250 | (afsr & PSYCHO_CEAFSR_MID) >> 24UL, |
| 251 | ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); |
David S. Miller | 6c108f1 | 2007-05-07 23:49:01 -0700 | [diff] [blame] | 252 | printk("%s: CE AFAR [%016lx]\n", pbm->name, afar); |
| 253 | printk("%s: CE Secondary errors [", pbm->name); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | reported = 0; |
| 255 | if (afsr & PSYCHO_CEAFSR_SPIO) { |
| 256 | reported++; |
| 257 | printk("(PIO)"); |
| 258 | } |
| 259 | if (afsr & PSYCHO_CEAFSR_SDRD) { |
| 260 | reported++; |
| 261 | printk("(DMA Read)"); |
| 262 | } |
| 263 | if (afsr & PSYCHO_CEAFSR_SDWR) { |
| 264 | reported++; |
| 265 | printk("(DMA Write)"); |
| 266 | } |
| 267 | if (!reported) |
| 268 | printk("(none)"); |
| 269 | printk("]\n"); |
| 270 | |
| 271 | return IRQ_HANDLED; |
| 272 | } |
| 273 | |
| 274 | /* PCI Errors. They are signalled by the PCI bus module since they |
| 275 | * are associated with a specific bus segment. |
| 276 | */ |
| 277 | #define PSYCHO_PCI_AFSR_A 0x2010UL |
| 278 | #define PSYCHO_PCI_AFSR_B 0x4010UL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | #define PSYCHO_PCI_AFAR_A 0x2018UL |
| 280 | #define PSYCHO_PCI_AFAR_B 0x4018UL |
| 281 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | /* XXX What about PowerFail/PowerManagement??? -DaveM */ |
| 283 | #define PSYCHO_ECC_CTRL 0x0020 |
| 284 | #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ |
| 285 | #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ |
| 286 | #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 287 | static void psycho_register_error_handlers(struct pci_pbm_info *pbm) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | { |
Grant Likely | cd4cd73 | 2010-07-22 16:04:30 -0600 | [diff] [blame] | 289 | struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node); |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 290 | unsigned long base = pbm->controller_regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | u64 tmp; |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 292 | int err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 294 | if (!op) |
| 295 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 297 | /* Psycho interrupt property order is: |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 298 | * 0: PCIERR INO for this PBM |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 299 | * 1: UE ERR |
| 300 | * 2: CE ERR |
| 301 | * 3: POWER FAIL |
| 302 | * 4: SPARE HARDWARE |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 303 | * 5: POWER MANAGEMENT |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 304 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | |
Grant Likely | 1636f8a | 2010-06-18 11:09:58 -0600 | [diff] [blame] | 306 | if (op->archdata.num_irqs < 6) |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 307 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 308 | |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 309 | /* We really mean to ignore the return result here. Two |
| 310 | * PCI controller share the same interrupt numbers and |
David S. Miller | a0381a9 | 2009-01-02 19:12:46 -0800 | [diff] [blame] | 311 | * drive the same front-end hardware. |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 312 | */ |
Grant Likely | 1636f8a | 2010-06-18 11:09:58 -0600 | [diff] [blame] | 313 | err = request_irq(op->archdata.irqs[1], psycho_ue_intr, IRQF_SHARED, |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 314 | "PSYCHO_UE", pbm); |
Grant Likely | 1636f8a | 2010-06-18 11:09:58 -0600 | [diff] [blame] | 315 | err = request_irq(op->archdata.irqs[2], psycho_ce_intr, IRQF_SHARED, |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 316 | "PSYCHO_CE", pbm); |
| 317 | |
| 318 | /* This one, however, ought not to fail. We can just warn |
| 319 | * about it since the system can still operate properly even |
| 320 | * if this fails. |
| 321 | */ |
Grant Likely | 1636f8a | 2010-06-18 11:09:58 -0600 | [diff] [blame] | 322 | err = request_irq(op->archdata.irqs[0], psycho_pcierr_intr, IRQF_SHARED, |
David S. Miller | af80318 | 2007-05-08 17:23:31 -0700 | [diff] [blame] | 323 | "PSYCHO_PCIERR", pbm); |
| 324 | if (err) |
| 325 | printk(KERN_WARNING "%s: Could not register PCIERR, " |
| 326 | "err=%d\n", pbm->name, err); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | |
| 328 | /* Enable UE and CE interrupts for controller. */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 329 | upa_writeq((PSYCHO_ECCCTRL_EE | |
| 330 | PSYCHO_ECCCTRL_UE | |
| 331 | PSYCHO_ECCCTRL_CE), base + PSYCHO_ECC_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | |
| 333 | /* Enable PCI Error interrupts and clear error |
| 334 | * bits for each PBM. |
| 335 | */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 336 | tmp = upa_readq(base + PSYCHO_PCIA_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 338 | PSYCHO_PCICTRL_SBH_ERR | |
| 339 | PSYCHO_PCICTRL_EEN); |
| 340 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 341 | upa_writeq(tmp, base + PSYCHO_PCIA_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 343 | tmp = upa_readq(base + PSYCHO_PCIB_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 345 | PSYCHO_PCICTRL_SBH_ERR | |
| 346 | PSYCHO_PCICTRL_EEN); |
| 347 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 348 | upa_writeq(tmp, base + PSYCHO_PCIB_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | /* PSYCHO boot time probing and initialization. */ |
David S. Miller | 085ae41 | 2005-08-08 13:19:08 -0700 | [diff] [blame] | 352 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | { |
| 354 | u8 *addr; |
| 355 | |
| 356 | /* Set cache-line size to 64 bytes, this is actually |
| 357 | * a nop but I do it for completeness. |
| 358 | */ |
| 359 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 360 | 0, PCI_CACHE_LINE_SIZE); |
| 361 | pci_config_write8(addr, 64 / sizeof(u32)); |
| 362 | |
| 363 | /* Set PBM latency timer to 64 PCI clocks. */ |
| 364 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 365 | 0, PCI_LATENCY_TIMER); |
| 366 | pci_config_write8(addr, 64); |
| 367 | } |
| 368 | |
Sam Ravnborg | b7c13f7 | 2013-01-01 16:02:33 +0100 | [diff] [blame] | 369 | static void psycho_scan_bus(struct pci_pbm_info *pbm, |
| 370 | struct device *parent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | { |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 372 | pbm_config_busmastering(pbm); |
| 373 | pbm->is_66mhz_capable = 0; |
David S. Miller | e822358a | 2008-09-01 18:32:22 -0700 | [diff] [blame] | 374 | pbm->pci_bus = pci_scan_one_pbm(pbm, parent); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | |
| 376 | /* After the PCI bus scan is complete, we can register |
| 377 | * the error interrupt handlers. |
| 378 | */ |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 379 | psycho_register_error_handlers(pbm); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | } |
| 381 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 382 | #define PSYCHO_IRQ_RETRY 0x1a00UL |
| 383 | #define PSYCHO_PCIA_DIAG 0x2020UL |
| 384 | #define PSYCHO_PCIB_DIAG 0x4020UL |
| 385 | #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ |
| 386 | #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ |
| 387 | #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ |
| 388 | #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ |
| 389 | #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ |
| 390 | #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ |
| 391 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ |
| 392 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ |
| 393 | |
David S. Miller | 28113a9 | 2007-05-08 00:19:02 -0700 | [diff] [blame] | 394 | static void psycho_controller_hwinit(struct pci_pbm_info *pbm) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | { |
| 396 | u64 tmp; |
| 397 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 398 | upa_writeq(5, pbm->controller_regs + PSYCHO_IRQ_RETRY); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | |
| 400 | /* Enable arbiter for all PCI slots. */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 401 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 402 | tmp |= PSYCHO_PCICTRL_AEN; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 403 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 405 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 406 | tmp |= PSYCHO_PCICTRL_AEN; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 407 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_CTRL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 408 | |
| 409 | /* Disable DMA write / PIO read synchronization on |
| 410 | * both PCI bus segments. |
| 411 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] |
| 412 | */ |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 413 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIA_DIAG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 414 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 415 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIA_DIAG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 417 | tmp = upa_readq(pbm->controller_regs + PSYCHO_PCIB_DIAG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 418 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 419 | upa_writeq(tmp, pbm->controller_regs + PSYCHO_PCIB_DIAG); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 420 | } |
| 421 | |
David S. Miller | 28113a9 | 2007-05-08 00:19:02 -0700 | [diff] [blame] | 422 | static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | int is_pbm_a) |
| 424 | { |
| 425 | unsigned long base = pbm->controller_regs; |
| 426 | u64 control; |
| 427 | |
| 428 | if (is_pbm_a) { |
| 429 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; |
| 430 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; |
| 431 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 432 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_A; |
| 433 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_A; |
| 434 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_A; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 435 | } else { |
| 436 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; |
| 437 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; |
| 438 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 439 | pbm->stc.strbuf_err_stat = base + PSYCHO_STC_ERR_B; |
| 440 | pbm->stc.strbuf_tag_diag = base + PSYCHO_STC_TAG_B; |
| 441 | pbm->stc.strbuf_line_diag= base + PSYCHO_STC_LINE_B; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | } |
| 443 | /* PSYCHO's streaming buffer lacks ctx flushing. */ |
| 444 | pbm->stc.strbuf_ctxflush = 0; |
| 445 | pbm->stc.strbuf_ctxmatch_base = 0; |
| 446 | |
| 447 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) |
| 448 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) |
| 449 | + 63UL) |
| 450 | & ~63UL); |
| 451 | pbm->stc.strbuf_flushflag_pa = (unsigned long) |
| 452 | __pa(pbm->stc.strbuf_flushflag); |
| 453 | |
| 454 | /* Enable the streaming buffer. We have to be careful |
| 455 | * just in case OBP left it with LRU locking enabled. |
| 456 | * |
| 457 | * It is possible to control if PBM will be rerun on |
| 458 | * line misses. Currently I just retain whatever setting |
| 459 | * OBP left us with. All checks so far show it having |
| 460 | * a value of zero. |
| 461 | */ |
| 462 | #undef PSYCHO_STRBUF_RERUN_ENABLE |
| 463 | #undef PSYCHO_STRBUF_RERUN_DISABLE |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 464 | control = upa_readq(pbm->stc.strbuf_control); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 465 | control |= PSYCHO_STRBUF_CTRL_ENAB; |
| 466 | control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); |
| 467 | #ifdef PSYCHO_STRBUF_RERUN_ENABLE |
| 468 | control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); |
| 469 | #else |
| 470 | #ifdef PSYCHO_STRBUF_RERUN_DISABLE |
| 471 | control |= PSYCHO_STRBUF_CTRL_RRDIS; |
| 472 | #endif |
| 473 | #endif |
David S. Miller | 87395fc | 2008-09-10 04:13:10 -0700 | [diff] [blame] | 474 | upa_writeq(control, pbm->stc.strbuf_control); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 475 | |
| 476 | pbm->stc.strbuf_enabled = 1; |
| 477 | } |
| 478 | |
| 479 | #define PSYCHO_IOSPACE_A 0x002000000UL |
| 480 | #define PSYCHO_IOSPACE_B 0x002010000UL |
| 481 | #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL |
| 482 | #define PSYCHO_MEMSPACE_A 0x100000000UL |
| 483 | #define PSYCHO_MEMSPACE_B 0x180000000UL |
| 484 | #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL |
| 485 | |
Sam Ravnborg | b7c13f7 | 2013-01-01 16:02:33 +0100 | [diff] [blame] | 486 | static void psycho_pbm_init(struct pci_pbm_info *pbm, |
| 487 | struct platform_device *op, int is_pbm_a) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 488 | { |
David S. Miller | 1c03a55 | 2008-09-10 03:15:56 -0700 | [diff] [blame] | 489 | psycho_pbm_init_common(pbm, op, "PSYCHO", PBM_CHIP_TYPE_PSYCHO); |
David S. Miller | 28113a9 | 2007-05-08 00:19:02 -0700 | [diff] [blame] | 490 | psycho_pbm_strbuf_init(pbm, is_pbm_a); |
David S. Miller | e822358a | 2008-09-01 18:32:22 -0700 | [diff] [blame] | 491 | psycho_scan_bus(pbm, &op->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 492 | } |
| 493 | |
Sam Ravnborg | b7c13f7 | 2013-01-01 16:02:33 +0100 | [diff] [blame] | 494 | static struct pci_pbm_info *psycho_find_sibling(u32 upa_portid) |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 495 | { |
| 496 | struct pci_pbm_info *pbm; |
| 497 | |
| 498 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) { |
| 499 | if (pbm->portid == upa_portid) |
| 500 | return pbm; |
| 501 | } |
| 502 | return NULL; |
| 503 | } |
| 504 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 505 | #define PSYCHO_CONFIGSPACE 0x001000000UL |
| 506 | |
Sam Ravnborg | b7c13f7 | 2013-01-01 16:02:33 +0100 | [diff] [blame] | 507 | static int psycho_probe(struct platform_device *op) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | { |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 509 | const struct linux_prom64_registers *pr_regs; |
Grant Likely | 61c7a08 | 2010-04-13 16:12:29 -0700 | [diff] [blame] | 510 | struct device_node *dp = op->dev.of_node; |
David S. Miller | 34768bc | 2007-05-07 23:06:27 -0700 | [diff] [blame] | 511 | struct pci_pbm_info *pbm; |
David S. Miller | 16ce82d | 2007-04-26 21:08:21 -0700 | [diff] [blame] | 512 | struct iommu *iommu; |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 513 | int is_pbm_a, err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 514 | u32 upa_portid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | |
David S. Miller | 0f73d1b | 2008-09-01 20:18:04 -0700 | [diff] [blame] | 516 | upa_portid = of_getintprop_default(dp, "upa-portid", 0xff); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 517 | |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 518 | err = -ENOMEM; |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 519 | pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); |
| 520 | if (!pbm) { |
| 521 | printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n"); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 522 | goto out_err; |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 523 | } |
| 524 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 525 | pbm->sibling = psycho_find_sibling(upa_portid); |
| 526 | if (pbm->sibling) { |
| 527 | iommu = pbm->sibling->iommu; |
| 528 | } else { |
| 529 | iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); |
| 530 | if (!iommu) { |
| 531 | printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n"); |
| 532 | goto out_free_controller; |
| 533 | } |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 534 | } |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 535 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 536 | pbm->iommu = iommu; |
| 537 | pbm->portid = upa_portid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 539 | pr_regs = of_get_property(dp, "reg", NULL); |
| 540 | err = -ENODEV; |
| 541 | if (!pr_regs) { |
| 542 | printk(KERN_ERR PFX "No reg property.\n"); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 543 | goto out_free_iommu; |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 544 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 546 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
David S. Miller | ad7ad57 | 2007-07-27 22:39:14 -0700 | [diff] [blame] | 547 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 548 | pbm->controller_regs = pr_regs[2].phys_addr; |
| 549 | pbm->config_space = (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); |
| 550 | |
| 551 | if (is_pbm_a) { |
| 552 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_A; |
| 553 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_A; |
| 554 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIA_CTRL; |
| 555 | } else { |
| 556 | pbm->pci_afsr = pbm->controller_regs + PSYCHO_PCI_AFSR_B; |
| 557 | pbm->pci_afar = pbm->controller_regs + PSYCHO_PCI_AFAR_B; |
| 558 | pbm->pci_csr = pbm->controller_regs + PSYCHO_PCIB_CTRL; |
| 559 | } |
| 560 | |
| 561 | psycho_controller_hwinit(pbm); |
| 562 | if (!pbm->sibling) { |
David S. Miller | a21cff3 | 2008-09-10 03:07:03 -0700 | [diff] [blame] | 563 | err = psycho_iommu_init(pbm, 128, 0xc0000000, |
| 564 | 0xffffffff, PSYCHO_CONTROL); |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 565 | if (err) |
| 566 | goto out_free_iommu; |
David S. Miller | a21cff3 | 2008-09-10 03:07:03 -0700 | [diff] [blame] | 567 | |
| 568 | /* If necessary, hook us up for starfire IRQ translations. */ |
| 569 | if (this_is_starfire) |
| 570 | starfire_hookup(pbm->portid); |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 571 | } |
| 572 | |
| 573 | psycho_pbm_init(pbm, op, is_pbm_a); |
| 574 | |
David S. Miller | 1c03a55 | 2008-09-10 03:15:56 -0700 | [diff] [blame] | 575 | pbm->next = pci_pbm_root; |
| 576 | pci_pbm_root = pbm; |
| 577 | |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 578 | if (pbm->sibling) |
| 579 | pbm->sibling->sibling = pbm; |
| 580 | |
| 581 | dev_set_drvdata(&op->dev, pbm); |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 582 | |
| 583 | return 0; |
| 584 | |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 585 | out_free_iommu: |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 586 | if (!pbm->sibling) |
| 587 | kfree(pbm->iommu); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 588 | |
| 589 | out_free_controller: |
David S. Miller | d3ae4b5 | 2008-09-09 23:54:02 -0700 | [diff] [blame] | 590 | kfree(pbm); |
David S. Miller | d7472c3 | 2008-08-31 01:33:52 -0700 | [diff] [blame] | 591 | |
| 592 | out_err: |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 593 | return err; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | } |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 595 | |
David S. Miller | 3628aa0 | 2011-03-30 17:37:56 -0700 | [diff] [blame] | 596 | static const struct of_device_id psycho_match[] = { |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 597 | { |
| 598 | .name = "pci", |
| 599 | .compatible = "pci108e,8000", |
| 600 | }, |
| 601 | {}, |
| 602 | }; |
| 603 | |
Grant Likely | 4ebb24f | 2011-02-22 20:01:33 -0700 | [diff] [blame] | 604 | static struct platform_driver psycho_driver = { |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 605 | .driver = { |
| 606 | .name = DRIVER_NAME, |
| 607 | .owner = THIS_MODULE, |
| 608 | .of_match_table = psycho_match, |
| 609 | }, |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 610 | .probe = psycho_probe, |
| 611 | }; |
| 612 | |
| 613 | static int __init psycho_init(void) |
| 614 | { |
Grant Likely | 4ebb24f | 2011-02-22 20:01:33 -0700 | [diff] [blame] | 615 | return platform_driver_register(&psycho_driver); |
David S. Miller | b20bfe4 | 2008-08-30 03:13:20 -0700 | [diff] [blame] | 616 | } |
| 617 | |
| 618 | subsys_initcall(psycho_init); |