tree 04e9f7baf7db1c2f1b7d49af72e353a5ecc1e2f4
parent ec4f9945b5b3e9e491a04eb1efe1c959371fa6de
author Josh Boyer <jwboyer@linux.vnet.ibm.com> 1220501300 +0000
committer Josh Boyer <jwboyer@linux.vnet.ibm.com> 1222780995 -0400

ibm_newemac: MAL support for PowerPC 405EZ

The PowerPC 405EZ SoC has some differences in the interrupt layout and
handling for the MAL.  The SERR, TXDE, and RXDE interrupts are OR'd into
a single interrupt.  Also, due to the possibility for interrupt coalescing,
the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in
the ICINTSTAT SDR.

This sets the proper MAL feature bits for 405EZ boards, and adds a common
shared handler for SERR, TXDE, and RXDE.  The defines for the ICINTSTAT DCR
are added to the proper header file as well.

This has been adapted from code originally written by Stefan Roese.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>