| commit | eb662f854710e6a438789a4b0d1d0cce8c12379d | [log] [tgz] |
|---|---|---|
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | Mon Sep 21 13:32:43 2015 +0200 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Wed Oct 21 21:51:28 2015 +0200 |
| tree | 1550ceffb453194a49357c0321b0c6dd56b279ba | |
| parent | 460d0d444822e9032a2573fc051b45c68b89a97a [diff] |
clk: sunxi: pll2: Add A13 support The A13, unlike the A10 and A20, doesn't use a pass-through exception for the 0 value in the pre and post dividers, but increments all the values written in the register by one. Add an exception for both these cases to handle them nicely. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>