| /* |
| * Copyright (c) 2019 MediaTek Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /* TOPCKGEN */ |
| #define TOP_MUX_AXI 1 |
| #define TOP_MUX_SPM 2 |
| #define TOP_MUX_SCP 3 |
| #define TOP_MUX_BUS_AXIMEM 4 |
| #define TOP_MUX_DISP 5 |
| #define TOP_MUX_MDP 6 |
| #define TOP_MUX_IMG1 7 |
| #define TOP_MUX_IMG2 8 |
| #define TOP_MUX_IPE 9 |
| #define TOP_MUX_DPE 10 |
| #define TOP_MUX_CAM 11 |
| #define TOP_MUX_CCU 12 |
| #define TOP_MUX_DSP 13 |
| #define TOP_MUX_DSP1 14 |
| #define TOP_MUX_DSP2 15 |
| #define TOP_MUX_DSP2_NPUPLL 16 |
| #define TOP_MUX_DSP5 17 |
| #define TOP_MUX_DSP5_APUPLL 18 |
| #define TOP_MUX_DSP7 19 |
| #define TOP_MUX_IPU_IF 20 |
| #define TOP_MUX_MFG_PLL 21 |
| #define TOP_MUX_MFG_REF 22 |
| #define TOP_MUX_CAMTG 23 |
| #define TOP_MUX_CAMTG2 24 |
| #define TOP_MUX_CAMTG3 25 |
| #define TOP_MUX_CAMTG4 26 |
| #define TOP_MUX_CAMTG5 27 |
| #define TOP_MUX_CAMTG6 28 |
| #define TOP_MUX_UART 29 |
| #define TOP_MUX_SPI 30 |
| #define TOP_MUX_MSDC50_0_HCLK 31 |
| #define TOP_MUX_MSDC50_0 32 |
| #define TOP_MUX_MSDC30_1 33 |
| #define TOP_MUX_MSDC30_2 34 |
| #define TOP_MUX_AUDIO 35 |
| #define TOP_MUX_AUD_INTBUS 36 |
| #define TOP_MUX_PWRAP_ULPOSC 37 |
| #define TOP_MUX_ATB 38 |
| #define TOP_MUX_SSPM 39 |
| #define TOP_MUX_DPI 40 |
| #define TOP_MUX_SCAM 41 |
| #define TOP_MUX_DISP_PWM 42 |
| #define TOP_MUX_USB_TOP 43 |
| #define TOP_MUX_SSUSB_XHCI 44 |
| #define TOP_MUX_I2C 45 |
| #define TOP_MUX_SENINF 46 |
| #define TOP_MUX_SENINF1 47 |
| #define TOP_MUX_SENINF2 48 |
| #define TOP_MUX_SENINF3 49 |
| #define TOP_MUX_TL 50 |
| #define TOP_MUX_DXCC 51 |
| #define TOP_MUX_AUD_ENGEN1 52 |
| #define TOP_MUX_AUD_ENGEN2 53 |
| #define TOP_MUX_AES_UFSFDE 54 |
| #define TOP_MUX_UFS 55 |
| #define TOP_MUX_AUD_1 56 |
| #define TOP_MUX_AUD_2 57 |
| #define TOP_MUX_ADSP 58 |
| #define TOP_MUX_DPMAIF_MAIN 59 |
| #define TOP_MUX_VENC 60 |
| #define TOP_MUX_VDEC 61 |
| #define TOP_MUX_CAMTM 62 |
| #define TOP_MUX_PWM 63 |
| #define TOP_MUX_AUDIO_H 64 |
| #define TOP_MUX_MCUPM 65 |
| #define TOP_MUX_SPMI_MST 66 |
| #define TOP_MUX_DVFSRC 67 |
| #define TOP_MUX_AES_MSDCFDE 68 |
| #define TOP_MUX_SFLASH 69 |
| #define TOP_MAINPLL_CK 70 |
| #define TOP_MAINPLL_D3 71 |
| #define TOP_MAINPLL_D4 72 |
| #define TOP_MAINPLL_D4_D2 73 |
| #define TOP_MAINPLL_D4_D4 74 |
| #define TOP_MAINPLL_D4_D8 75 |
| #define TOP_MAINPLL_D4_D16 76 |
| #define TOP_MAINPLL_D5 77 |
| #define TOP_MAINPLL_D5_D2 78 |
| #define TOP_MAINPLL_D5_D4 79 |
| #define TOP_MAINPLL_D5_D8 80 |
| #define TOP_MAINPLL_D6 81 |
| #define TOP_MAINPLL_D6_D2 82 |
| #define TOP_MAINPLL_D6_D4 83 |
| #define TOP_MAINPLL_D7 84 |
| #define TOP_MAINPLL_D7_D2 85 |
| #define TOP_MAINPLL_D7_D4 86 |
| #define TOP_MAINPLL_D7_D8 87 |
| #define TOP_UNIVPLL_CK 88 |
| #define TOP_UNIVPLL_D3 89 |
| #define TOP_UNIVPLL_D4 90 |
| #define TOP_UNIVPLL_D4_D2 91 |
| #define TOP_UNIVPLL_D4_D4 92 |
| #define TOP_UNIVPLL_D4_D8 93 |
| #define TOP_UNIVPLL_D5 94 |
| #define TOP_UNIVPLL_D5_D2 95 |
| #define TOP_UNIVPLL_D5_D4 96 |
| #define TOP_UNIVPLL_D5_D8 97 |
| #define TOP_UNIVPLL_D6 98 |
| #define TOP_UNIVPLL_D6_D2 99 |
| #define TOP_UNIVPLL_D6_D4 100 |
| #define TOP_UNIVPLL_D6_D8 101 |
| #define TOP_UNIVPLL_D6_D16 102 |
| #define TOP_UNIVPLL_D7 103 |
| #define TOP_APLL1_CK 104 |
| #define TOP_APLL1_D2 105 /* add manually */ |
| #define TOP_APLL1_D4 106 /* add manually */ |
| #define TOP_APLL1_D8 107 /* add manually */ |
| #define TOP_APLL2_CK 108 |
| #define TOP_APLL2_D2 109 /* add manually */ |
| #define TOP_APLL2_D4 110 /* add manually */ |
| #define TOP_APLL2_D8 111 /* add manually */ |
| #define TOP_MMPLL_D4 112 |
| #define TOP_MMPLL_D4_D2 113 |
| #define TOP_MMPLL_D5 114 |
| #define TOP_MMPLL_D5_D2 115 |
| #define TOP_MMPLL_D6 116 |
| #define TOP_MMPLL_D6_D2 117 |
| #define TOP_MMPLL_D7 118 |
| #define TOP_MMPLL_D9 119 |
| #define TOP_APUPLL_CK 120 |
| #define TOP_NPUPLL_CK 121 |
| #define TOP_USBPLL_CK 122 |
| #define TOP_TVDPLL_CK 123 |
| #define TOP_TVDPLL_D2 124 |
| #define TOP_TVDPLL_D4 125 |
| #define TOP_TVDPLL_D8 126 |
| #define TOP_TVDPLL_D16 127 |
| #define TOP_MSDCPLL_CK 128 |
| #define TOP_MSDCPLL_D2 129 |
| #define TOP_MSDCPLL_D4 130 |
| #define TOP_AD_OSC_CK 131 |
| #define TOP_OSC_D2 132 |
| #define TOP_OSC_D4 133 |
| #define TOP_OSC_D8 134 |
| #define TOP_OSC_D10 135 |
| #define TOP_OSC_D16 136 |
| #define TOP_OSC_D20 137 |
| #define TOP_CLK26M 138 /* add manually */ |
| #define TOP_CLK13M 139 /* add manually */ |
| #define TOP_F26M_CK_D2 140//used /* add manually */ |
| #define TOP_UNIVP_192M_CK 141 /* add manually */ |
| #define TOP_UNIVP_192M_D2 142 /* add manually */ |
| #define TOP_UNIVP_192M_D4 143 /* add manually */ |
| #define TOP_UNIVP_192M_D8 144 /* add manually */ |
| #define TOP_UNIVP_192M_D16 145 /* add manually */ |
| #define TOP_UNIVP_192M_D32 146 /* add manually */ |
| #define TOP_MFGPLL_CK 147 /* add manually */ |
| #define TOP_ADSPPLL_CK 148 /* add manually */ |
| #define TOP_I2S0_M_SEL 149 /* add manually */ |
| #define TOP_I2S1_M_SEL 150 /* add manually */ |
| #define TOP_I2S2_M_SEL 151 /* add manually */ |
| #define TOP_I2S3_M_SEL 152 /* add manually */ |
| #define TOP_I2S4_M_SEL 153 /* add manually */ |
| #define TOP_I2S5_M_SEL 154 /* add manually */ |
| #define TOP_I2S6_M_SEL 155 /* add manually */ |
| #define TOP_I2S7_M_SEL 156 /* add manually */ |
| #define TOP_I2S8_M_SEL 157 /* add manually */ |
| #define TOP_I2S9_M_SEL 158 /* add manually */ |
| #define TOP_APLL12_DIV0 159 /* add manually */ |
| #define TOP_APLL12_DIV1 160 /* add manually */ |
| #define TOP_APLL12_DIV2 161 /* add manually */ |
| #define TOP_APLL12_DIV3 162 /* add manually */ |
| #define TOP_APLL12_DIV4 163 /* add manually */ |
| #define TOP_APLL12_DIVB 164 /* add manually */ |
| #define TOP_APLL12_DIV5 165 /* add manually */ |
| #define TOP_APLL12_DIV6 166 /* add manually */ |
| #define TOP_APLL12_DIV7 167 /* add manually */ |
| #define TOP_APLL12_DIV8 168 /* add manually */ |
| #define TOP_APLL12_DIV9 169 /* add manually */ |
| #define TOP_MUX_DSP1_NPUPLL 170 |
| #define TOP_NR_CLK 171 |
| |
| /* APMIXED */ |
| #define APMIXED_MAINPLL 1 |
| #define APMIXED_UNIVPLL 2 |
| #define APMIXED_MSDCPLL 3 |
| #define APMIXED_MMPLL 4 |
| #define APMIXED_ADSPPLL 5 |
| #define APMIXED_MFGPLL 6 |
| #define APMIXED_TVDPLL 7 |
| #define APMIXED_APLL1 8 |
| #define APMIXED_APLL2 9 |
| #define APMIXED_APUPLL 10 |
| #define APMIXED_NPUPLL 11 |
| #define APMIXED_USBPLL 12 |
| #define APMIXED_MIPID0_26M 13 |
| #define APMIXED_NR_CLK 14 |
| |
| /* APU0 */ |
| #define APU0_APU_CG 1 |
| #define APU0_AXI_M_CG 2 |
| #define APU0_JTAG_CG 3 |
| #define APU0_NR_CLK 4 |
| /* APU1 */ |
| #define APU1_APU_CG 1 |
| #define APU1_AXI_M_CG 2 |
| #define APU1_JTAG_CG 3 |
| #define APU1_NR_CLK 4 |
| /* APUSYS_VCORE */ |
| #define APUSYS_VCORE_AHB_CG 1 |
| #define APUSYS_VCORE_AXI_CG 2 |
| #define APUSYS_VCORE_ADL_CG 3 |
| #define APUSYS_VCORE_QOS_CG 4 |
| #define APUSYS_VCORE_NR_CLK 5 |
| /* APU_CONN */ |
| #define APU_CONN_APU_CG 1 |
| #define APU_CONN_AHB_CG 2 |
| #define APU_CONN_AXI_CG 3 |
| #define APU_CONN_ISP_CG 4 |
| #define APU_CONN_CAM_ADL_CG 5 |
| #define APU_CONN_IMG_ADL_CG 6 |
| #define APU_CONN_EMI_26M_CG 7 |
| #define APU_CONN_VPU_UDI_CG 8 |
| #define APU_CONN_EDMA_0_CG 9 |
| #define APU_CONN_EDMA_1_CG 10 |
| #define APU_CONN_EDMAL_0_CG 11 |
| #define APU_CONN_EDMAL_1_CG 12 |
| #define APU_CONN_MNOC_CG 13 |
| #define APU_CONN_TCM_CG 14 |
| #define APU_CONN_MD32_CG 15 |
| #define APU_CONN_IOMMU_0_CG 16 |
| #define APU_CONN_IOMMU_1_CG 17 |
| #define APU_CONN_MD32_32K_CG 18 |
| #define APU_CONN_NR_CLK 19 |
| |
| /* APU_MDLA0 */ |
| #define APU_MDLA0_MDLA_CG0 1 |
| #define APU_MDLA0_MDLA_CG1 2 |
| #define APU_MDLA0_MDLA_CG2 3 |
| #define APU_MDLA0_MDLA_CG3 4 |
| #define APU_MDLA0_MDLA_CG4 5 |
| #define APU_MDLA0_MDLA_CG5 6 |
| #define APU_MDLA0_MDLA_CG6 7 |
| #define APU_MDLA0_MDLA_CG7 8 |
| #define APU_MDLA0_MDLA_CG8 9 |
| #define APU_MDLA0_MDLA_CG9 10 |
| #define APU_MDLA0_MDLA_CG10 11 |
| #define APU_MDLA0_MDLA_CG11 12 |
| #define APU_MDLA0_MDLA_CG12 13 |
| #define APU_MDLA0_APB_CG 14 |
| #define APU_MDLA0_AXI_M_CG 15 |
| #define APU_MDLA0_NR_CLK 16 |
| |
| /* AUDIO */ |
| #define AUDIO_PDN_AFE 1 |
| #define AUDIO_PDN_22M 2 |
| #define AUDIO_PDN_24M 3 |
| #define AUDIO_PDN_APLL2_TUNER 4 |
| #define AUDIO_PDN_APLL_TUNER 5 |
| #define AUDIO_PDN_TDM_CK 6 |
| #define AUDIO_PDN_ADC 7 |
| #define AUDIO_PDN_DAC 8 |
| #define AUDIO_PDN_DAC_PREDIS 9 |
| #define AUDIO_PDN_TML 10 |
| #define AUDIO_PDN_NLE 11 |
| #define AUDIO_I2S1_BCLK_SW_CG 12 |
| #define AUDIO_I2S2_BCLK_SW_CG 13 |
| #define AUDIO_I2S3_BCLK_SW_CG 14 |
| #define AUDIO_I2S4_BCLK_SW_CG 15 |
| #define AUDIO_PDN_CONNSYS_I2S_ASRC 16 |
| #define AUDIO_PDN_GENERAL1_ASRC 17 |
| #define AUDIO_PDN_GENERAL2_ASRC 18 |
| #define AUDIO_PDN_DAC_HIRES 19 |
| #define AUDIO_PDN_ADC_HIRES 20 |
| #define AUDIO_PDN_ADC_HIRES_TML 21 |
| #define AUDIO_PDN_ADDA6_ADC 22 |
| #define AUDIO_PDN_ADDA6_ADC_HIRES 23 |
| #define AUDIO_PDN_3RD_DAC 24 |
| #define AUDIO_PDN_3RD_DAC_PREDIS 25 |
| #define AUDIO_PDN_3RD_DAC_TML 26 |
| #define AUDIO_PDN_3RD_DAC_HIRES 27 |
| #define AUDIO_I2S5_BCLK_SW_CG 28 |
| #define AUDIO_I2S6_BCLK_SW_CG 29 |
| #define AUDIO_I2S7_BCLK_SW_CG 30 |
| #define AUDIO_I2S8_BCLK_SW_CG 31 |
| #define AUDIO_I2S9_BCLK_SW_CG 32 |
| #define AUDIO_NR_CLK 33 |
| |
| /* CAMSYS_MAIN */ |
| #define CAMSYS_MAIN_LARB13_CGPDN 1 |
| #define CAMSYS_MAIN_DFP_VAD_CGPDN 2 |
| #define CAMSYS_MAIN_CAM_CGPDN 3 |
| #define CAMSYS_MAIN_CAMTG_CGPDN 4 |
| #define CAMSYS_MAIN_LARB14_CGPDN 5 |
| #define CAMSYS_MAIN_SENINF_CGPDN 6 |
| #define CAMSYS_MAIN_CAMSV0_CGPDN 7 |
| #define CAMSYS_MAIN_CAMSV1_CGPDN 8 |
| #define CAMSYS_MAIN_CAMSV2_CGPDN 9 |
| #define CAMSYS_MAIN_CAMSV3_CGPDN 10 |
| #define CAMSYS_MAIN_CCU0_CGPDN 11 |
| #define CAMSYS_MAIN_CCU1_CGPDN 12 |
| #define CAMSYS_MAIN_MRAW0_CGPDN 13 |
| #define CAMSYS_MAIN_FAKE_ENG_CGPDN 14 |
| #define CAMSYS_MAIN_CCU_GALS_CGPDN 15 |
| #define CAMSYS_MAIN_CAM2MM_GALS_CGPDN 16 |
| #define CAMSYS_MAIN_NR_CLK 17 |
| /* CAMSYS_RAWA */ |
| #define CAMSYS_RAWA_LARBX_CGPDN 1 |
| #define CAMSYS_RAWA_CAM_CGPDN 2 |
| #define CAMSYS_RAWA_CAMTG_CGPDN 3 |
| #define CAMSYS_RAWA_NR_CLK 4 |
| /* CAMSYS_RAWB */ |
| #define CAMSYS_RAWB_LARBX_CGPDN 1 |
| #define CAMSYS_RAWB_CAM_CGPDN 2 |
| #define CAMSYS_RAWB_CAMTG_CGPDN 3 |
| #define CAMSYS_RAWB_NR_CLK 4 |
| /* CAMSYS_RAWC */ |
| #define CAMSYS_RAWC_LARBX_CGPDN 1 |
| #define CAMSYS_RAWC_CAM_CGPDN 2 |
| #define CAMSYS_RAWC_CAMTG_CGPDN 3 |
| #define CAMSYS_RAWC_NR_CLK 4 |
| |
| /* GCE */ |
| #define GCE_SW_CG_0 1 |
| #define GCE_NR_CLK 2 |
| |
| /* IMGSYS1 */ |
| #define IMGSYS1_LARB9_CGPDN 1 |
| #define IMGSYS1_LARB10_CGPDN 2 |
| #define IMGSYS1_DIP_CGPDN 3 |
| #define IMGSYS1_GALS_CGPDN 4 |
| #define IMGSYS1_NR_CLK 5 |
| /* IMGSYS2 */ |
| #define IMGSYS2_LARB11_CGPDN 1 |
| #define IMGSYS2_LARB12_CGPDN 2 |
| #define IMGSYS2_MFB_CGPDN 3 |
| #define IMGSYS2_WPE_CGPDN 4 |
| #define IMGSYS2_MSS_CGPDN 5 |
| #define IMGSYS2_GALS_CGPDN 6 |
| #define IMGSYS2_NR_CLK 7 |
| |
| /* IMP_IIC_WRAP_C */ |
| #define IMP_IIC_WRAP_C_AP_I2C10_CG_RO 1 |
| #define IMP_IIC_WRAP_C_AP_I2C11_CG_RO 2 |
| #define IMP_IIC_WRAP_C_AP_I2C12_CG_RO 3 |
| #define IMP_IIC_WRAP_C_AP_I2C13_CG_RO 4 |
| #define IMP_IIC_WRAP_C_NR_CLK 5 |
| /* IMP_IIC_WRAP_E */ |
| #define IMP_IIC_WRAP_E_AP_I2C3_CG_RO 1 |
| #define IMP_IIC_WRAP_E_NR_CLK 2 |
| /* IMP_IIC_WRAP_N */ |
| #define IMP_IIC_WRAP_N_AP_I2C0_CG_RO 1 |
| #define IMP_IIC_WRAP_N_AP_I2C6_CG_RO 2 |
| #define IMP_IIC_WRAP_N_NR_CLK 3 |
| /* IMP_IIC_WRAP_S */ |
| //#define IMP_IIC_WRAP_S_AP_I2C5_CG_RO 1 |
| #define IMP_IIC_WRAP_S_AP_I2C7_CG_RO 1 |
| #define IMP_IIC_WRAP_S_AP_I2C8_CG_RO 2 |
| #define IMP_IIC_WRAP_S_AP_I2C9_CG_RO 3 |
| #define IMP_IIC_WRAP_S_NR_CLK 4 |
| /* IMP_IIC_WRAP_W */ |
| //#define IMP_IIC_WRAP_W_AP_I2C0_CG_RO 1 |
| #define IMP_IIC_WRAP_W_AP_I2C5_CG_RO 1 |
| #define IMP_IIC_WRAP_W_NR_CLK 2 |
| /* IMP_IIC_WRAP_WS */ |
| //#define IMP_IIC_WRAP_WS_AP_I2C0_CG_RO 1 |
| #define IMP_IIC_WRAP_WS_AP_I2C1_CG_RO 1 |
| #define IMP_IIC_WRAP_WS_AP_I2C2_CG_RO 2 |
| #define IMP_IIC_WRAP_WS_AP_I2C4_CG_RO 3 |
| #define IMP_IIC_WRAP_WS_NR_CLK 4 |
| |
| /* INFRACFG_AO */ |
| #define INFRACFG_AO_PMIC_CG_TMR 1 |
| #define INFRACFG_AO_PMIC_CG_AP 2 |
| #define INFRACFG_AO_PMIC_CG_MD 3 |
| #define INFRACFG_AO_PMIC_CG_CONN 4 |
| #define INFRACFG_AO_SCPSYS_CG 5 |
| #define INFRACFG_AO_SEJ_CG 6 |
| #define INFRACFG_AO_APXGPT_CG 7 |
| #define INFRACFG_AO_MCUPM_CG 8 |
| #define INFRACFG_AO_GCE_CG 9 |
| #define INFRACFG_AO_GCE2_CG 10 |
| #define INFRACFG_AO_THERM_CG 11 |
| #define INFRACFG_AO_I2C0_CG 12 |
| #define INFRACFG_AO_I2C1_CG 13 |
| #define INFRACFG_AO_I2C2_CG 14 |
| #define INFRACFG_AO_I2C3_CG 15 |
| #define INFRACFG_AO_PWM_HCLK_CG 16 |
| #define INFRACFG_AO_PWM1_CG 17 |
| #define INFRACFG_AO_PWM2_CG 18 |
| #define INFRACFG_AO_PWM3_CG 19 |
| #define INFRACFG_AO_PWM4_CG 20 |
| #define INFRACFG_AO_PWM_CG 21 |
| #define INFRACFG_AO_UART0_CG 22 |
| #define INFRACFG_AO_UART1_CG 23 |
| #define INFRACFG_AO_UART2_CG 24 |
| #define INFRACFG_AO_UART3_CG 25 |
| #define INFRACFG_AO_GCE_26M 26 |
| #define INFRACFG_AO_CQ_DMA_FPC 27 |
| #define INFRACFG_AO_BTIF_CG 28 |
| #define INFRACFG_AO_MD2MD_CCIF3_CG 29 |
| #define INFRACFG_AO_SPI0_CG 30 |
| #define INFRACFG_AO_MSDC0_CG 31 |
| #define INFRACFG_AO_MSDC1_CG 32 |
| #define INFRACFG_AO_MSDC0_SRC_CLK_CG 33 |
| #define INFRACFG_AO_DVFSRC_CG 34 |
| #define INFRACFG_AO_GCPU_CG 35 |
| #define INFRACFG_AO_TRNG_CG 36 |
| #define INFRACFG_AO_AUXADC_CG 37 |
| #define INFRACFG_AO_CPUM_CG 38 |
| #define INFRACFG_AO_CCIF1_AP_CG 39 |
| #define INFRACFG_AO_CCIF1_MD_CG 40 |
| #define INFRACFG_AO_AUXADC_MD_CG 41 |
| #define INFRACFG_AO_PCIE_TL_CLK26M_CG 42 |
| #define INFRACFG_AO_MSDC1_SRC_CLK_CG 43 |
| #define INFRACFG_AO_PCIE_TL_CLK96M_CG 44 |
| #define INFRACFG_AO_PCIE_PL_PCLK250M_CG 45 |
| #define INFRACFG_AO_DEVICE_APC_CG 46 |
| #define INFRACFG_AO_CCIF_AP_CG 47 |
| #define INFRACFG_AO_DEBUGSYS_CG 48 |
| #define INFRACFG_AO_AUDIO_CG 49 |
| #define INFRACFG_AO_CCIF_MD_CG 50 |
| #define INFRACFG_AO_DXCC_SEC_CORE_CG 51 |
| #define INFRACFG_AO_DXCC_AO_CG 52 |
| #define INFRACFG_AO_DBG_TRACE_CG 53 |
| #define INFRACFG_AO_DEVMPU_BCLK_CG 54 |
| #define INFRACFG_AO_DRAMC_F26M_CG 55 |
| #define INFRACFG_AO_IRTX_CG 56 |
| #define INFRACFG_AO_SSUSB_CG 57 |
| #define INFRACFG_AO_DISP_PWM_CG 58 |
| #define INFRACFG_AO_CLDMA_BCLK_CK 59 |
| #define INFRACFG_AO_AUDIO_26M_BCLK_CK 60 |
| #define INFRACFG_AO_MODEM_TEMP_SHARE_CG 61 |
| #define INFRACFG_AO_SPI1_CG 62 |
| #define INFRACFG_AO_I2C4_CG 63 |
| #define INFRACFG_AO_SPI2_CG 64 |
| #define INFRACFG_AO_SPI3_CG 65 |
| #define INFRACFG_AO_UNIPRO_SYSCLK_CG 66 |
| #define INFRACFG_AO_UNIPRO_TICK_CG 67 |
| #define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 68 |
| #define INFRACFG_AO_MD32_BCLK_CG 69 |
| #define INFRACFG_AO_SSPM_CG 70 |
| #define INFRACFG_AO_UNIPRO_MBIST_CG 71 |
| #define INFRACFG_AO_SSPM_BUS_HCLK_CG 72 |
| #define INFRACFG_AO_I2C5_CG 73 |
| #define INFRACFG_AO_I2C5_ARBITER_CG 74 |
| #define INFRACFG_AO_I2C5_IMM_CG 75 |
| #define INFRACFG_AO_I2C1_ARBITER_CG 76 |
| #define INFRACFG_AO_I2C1_IMM_CG 77 |
| #define INFRACFG_AO_I2C2_ARBITER_CG 78 |
| #define INFRACFG_AO_I2C2_IMM_CG 79 |
| #define INFRACFG_AO_SPI4_CG 80 |
| #define INFRACFG_AO_SPI5_CG 81 |
| #define INFRACFG_AO_CQ_DMA_CG 82 |
| #define INFRACFG_AO_UFS_CG 83 |
| #define INFRACFG_AO_AES_UFSFDE_CG 84 |
| #define INFRACFG_AO_UFS_TICK_CG 85 |
| #define INFRACFG_AO_SSUSB_XHCI_CG 86 |
| #define INFRACFG_AO_MSDC0_SELF_CG 87 |
| #define INFRACFG_AO_MSDC1_SELF_CG 88 |
| #define INFRACFG_AO_MSDC2_SELF_CG 89 |
| #define INFRACFG_AO_SSPM_26M_SELF_CG 90 |
| #define INFRACFG_AO_SSPM_32K_SELF_CG 91 |
| #define INFRACFG_AO_UFS_AXI_CG 92 |
| #define INFRACFG_AO_I2C6_CG 93 |
| #define INFRACFG_AO_AP_MSDC0_CG 94 |
| #define INFRACFG_AO_MD_MSDC0_CG 95 |
| #define INFRACFG_AO_CCIF5_AP_CG 96 |
| #define INFRACFG_AO_CCIF5_MD_CG 97 |
| #define INFRACFG_AO_PCIE_TOP_HCLK133M_CG 98 |
| #define INFRACFG_AO_FLASHIF_TOP_HCLK133M_CG 99 |
| #define INFRACFG_AO_PCIE_PERI_CLK26M_CG 100 |
| #define INFRACFG_AO_CCIF2_AP_CG 101 |
| #define INFRACFG_AO_CCIF2_MD_CG 102 |
| #define INFRACFG_AO_CCIF3_AP_CG 103 |
| #define INFRACFG_AO_CCIF3_MD_CG 104 |
| #define INFRACFG_AO_SEJ_F13M_CG 105 |
| #define INFRACFG_AO_AES_CG 106 |
| #define INFRACFG_AO_I2C7_CG 107 |
| #define INFRACFG_AO_I2C8_CG 108 |
| #define INFRACFG_AO_FBIST2FPC_CG 109 |
| #define INFRACFG_AO_DEVICE_APC_SYNC_CG 110 |
| #define INFRACFG_AO_DPMAIF_MAIN_CG 111 |
| #define INFRACFG_AO_PCIE_TL_CLK32K_CG 112 |
| #define INFRACFG_AO_CCIF4_AP_CG 113 |
| #define INFRACFG_AO_CCIF4_MD_CG 114 |
| #define INFRACFG_AO_SPI6_CK_CG 115 |
| #define INFRACFG_AO_SPI7_CK_CG 116 |
| #define INFRACFG_AO_HF133M_MCLK_PERI_CG 117 |
| #define INFRACFG_AO_HF66M_MCLK_PERI_CG 118 |
| #define INFRACFG_AO_HD66M_PERIBUS_MCLK_PERI_CG 119 |
| #define INFRACFG_AO_FREE_DCM_133M_CG 120 |
| #define INFRACFG_AO_FREE_DCM_66M_CG 121 |
| #define INFRACFG_AO_PERIBUS_DCM_133M_CG 122 |
| #define INFRACFG_AO_PERIBUS_DCM_66M_CG 123 |
| #define INFRACFG_AO_PERITOP_PAR_WARP_CG 124 |
| #define INFRACFG_AO_PERITOP_PAR_WARP_CKCTL_CG 125 |
| #define INFRACFG_AO_FLASHIF_PERI_CLK26M_CG 126 |
| #define INFRACFG_AO_FLASHIF_SFLASH_CG 127 |
| #define INFRACFG_AO_AP_DMA_PSEUDO_CG 128/* add manually */ |
| #define INFRACFG_AO_AP_DMA_CG 129/* add manually */ |
| #define INFRACFG_AO_MSDC2_CG 130 |
| #define INFRACFG_AO_MSDC2_SRC_CLK_CG 131 |
| #define INFRACFG_AO_NR_CLK 132 |
| |
| /* IPESYS */ |
| #define IPESYS_LARB19_CGPDN 1 |
| #define IPESYS_LARB20_CGPDN 2 |
| #define IPESYS_IPE_SMI_SUBCOM_CGPDN 3 |
| #define IPESYS_FD_CGPDN 4 |
| #define IPESYS_FE_CGPDN 5 |
| #define IPESYS_RSC_CGPDN 6 |
| #define IPESYS_DPE_CGPDN 7 |
| #define IPESYS_GALS_CGPDN 8 |
| #define IPESYS_NR_CLK 9 |
| |
| /* MFGCFG */ |
| #define MFGCFG_BG3D 1 |
| #define MFGCFG_NR_CLK 2 |
| |
| /* MMSYS_CONFIG */ |
| #define MM_DISP_MUTEX0 1 |
| #define MM_DISP_CONFIG 2 |
| #define MM_DISP_OVL0 3 |
| #define MM_DISP_RDMA0 4 |
| #define MM_DISP_OVL0_2L 5 |
| #define MM_DISP_WDMA0 6 |
| #define MM_DISP_UFBC_WDMA0 7 |
| #define MM_DISP_RSZ0 8 |
| #define MM_DISP_AAL0 9 |
| #define MM_DISP_CCORR0 10 |
| #define MM_DISP_DITHER0 11 |
| #define MM_SMI_INFRA 12 |
| #define MM_DISP_GAMMA0 13 |
| #define MM_DISP_POSTMASK0 14 |
| #define MM_DISP_DSC_WRAP0 15 |
| #define MM_DSI0 16 |
| #define MM_DISP_COLOR0 17 |
| #define MM_SMI_COMMON 18 |
| #define MM_DISP_FAKE_ENG0 19 |
| #define MM_DISP_FAKE_ENG1 20 |
| #define MM_MDP_TDSHP4 21 |
| #define MM_MDP_RSZ4 22 |
| #define MM_MDP_AAL4 23 |
| #define MM_MDP_HDR4 24 |
| #define MM_MDP_RDMA4 25 |
| #define MM_MDP_COLOR4 26 |
| #define MM_DISP_Y2R0 27 |
| #define MM_SMI_GALS 28 |
| #define MM_DISP_OVL2_2L 29 |
| #define MM_DISP_RDMA4 30 |
| #define MM_DISP_DPI0 31 |
| #define MM_SMI_IOMMU 32 |
| #define MM_DSI_DSI0 33 |
| #define MM_DPI_DPI0 34 |
| #define MM_DP_INTF 35 |
| #define MM_26MHZ 36 |
| #define MM_32KHZ 37 |
| #define MM_NR_CLK 38 |
| |
| /* MSDC0 */ |
| #define MSDC0_AXI_WRAP_CKEN 1 |
| #define MSDC0_NR_CLK 2 |
| /* PERICFG */ |
| #define PERICFG_PERIAXI_CG_DISABLE 1 |
| #define PERICFG_NR_CLK 2 |
| |
| /* VDEC_CORE_GCON */ |
| #define VDEC_GCON_LARB1_CKEN 1 |
| #define VDEC_GCON_LAT_CKEN 2 |
| #define VDEC_GCON_LAT_ACTIVE 3 |
| #define VDEC_GCON_LAT_CKEN_ENG 4 |
| #define VDEC_GCON_VDEC_CKEN 5 |
| #define VDEC_GCON_VDEC_ACTIVE 6 |
| #define VDEC_GCON_VDEC_CKEN_ENG 7 |
| #define VDEC_GCON_NR_CLK 8 |
| /* VDEC_SOC_GCON */ |
| #define VDEC_SOC_GCON_LARB1_CKEN 1 |
| #define VDEC_SOC_GCON_LAT_CKEN 2 |
| #define VDEC_SOC_GCON_LAT_ACTIVE 3 |
| #define VDEC_SOC_GCON_LAT_CKEN_ENG 4 |
| #define VDEC_SOC_GCON_VDEC_CKEN 5 |
| #define VDEC_SOC_GCON_VDEC_ACTIVE 6 |
| #define VDEC_SOC_GCON_VDEC_CKEN_ENG 7 |
| #define VDEC_SOC_GCON_NR_CLK 8 |
| |
| /* VENC_GCON */ |
| #define VENC_GCON_SET0_LARB 1 |
| #define VENC_GCON_SET1_VENC 2 |
| #define VENC_GCON_SET2_JPGENC 3 |
| #define VENC_GCON_SET5_GALS 4 |
| #define VENC_GCON_NR_CLK 5 |
| |
| /* MSDCSYS */ |
| #define MSDC_AES_CK_0P_CKEN 1 |
| #define MSDC_SRC_CK_0P_CKEN 2 |
| #define MSDC_SRC_CK_1P_CKEN 3 |
| #define MSDC_SRC_CK_2P_CKEN 4 |
| #define MSDC_PCLK_CK_MSDC0_CKEN 5 |
| #define MSDC_PCLK_CK_MSDC1_CKEN 6 |
| #define MSDC_PCLK_CK_MSDC2_CKEN 7 |
| #define MSDC_PCLK_CK_CFG_CKEN 8 |
| #define MSDC_AXI_CK_CKEN 9 |
| #define MSDC_HCLK_MST_CK_0P_CKEN 10 |
| #define MSDC_HCLK_MST_CK_1P_CKEN 11 |
| #define MSDC_HCLK_MST_CK_2P_CKEN 12 |
| #define MSDC_MEM_OFF_DLY_26M_CK_CKEN 13 |
| #define MSDC_32K_CK_CKEN 14 |
| #define MSDC_AHB2AXI_BRG_AXI_CKEN 15 |
| #define MSDC_NR_CLK 16 |
| /* Note: TOPCK register offset definition is generated from parsing |
| * TOPCKGEN's register (project.h) with keyword "CLK_CFG_" |
| */ |
| /* #define TOPCKGEN_BASE 0x10000000 */ |
| |
| #define CLK_CFG_UPDATE 0x004 |
| #define CLK_CFG_UPDATE1 0x008 |
| #define CLK_CFG_UPDATE2 0x00c |
| #define CLK_CFG_0 0x010 |
| #define CLK_CFG_0_SET 0x014 |
| #define CLK_CFG_0_CLR 0x018 |
| #define CLK_CFG_1 0x020 |
| #define CLK_CFG_1_SET 0x024 |
| #define CLK_CFG_1_CLR 0x028 |
| #define CLK_CFG_2 0x030 |
| #define CLK_CFG_2_SET 0x034 |
| #define CLK_CFG_2_CLR 0x038 |
| #define CLK_CFG_3 0x040 |
| #define CLK_CFG_3_SET 0x044 |
| #define CLK_CFG_3_CLR 0x048 |
| #define CLK_CFG_4 0x050 |
| #define CLK_CFG_4_SET 0x054 |
| #define CLK_CFG_4_CLR 0x058 |
| #define CLK_CFG_5 0x060 |
| #define CLK_CFG_5_SET 0x064 |
| #define CLK_CFG_5_CLR 0x068 |
| #define CLK_CFG_6 0x070 |
| #define CLK_CFG_6_SET 0x074 |
| #define CLK_CFG_6_CLR 0x078 |
| #define CLK_CFG_7 0x080 |
| #define CLK_CFG_7_SET 0x084 |
| #define CLK_CFG_7_CLR 0x088 |
| #define CLK_CFG_8 0x090 |
| #define CLK_CFG_8_SET 0x094 |
| #define CLK_CFG_8_CLR 0x098 |
| #define CLK_CFG_9 0x0a0 |
| #define CLK_CFG_9_SET 0x0a4 |
| #define CLK_CFG_9_CLR 0x0a8 |
| #define CLK_CFG_10 0x0b0 |
| #define CLK_CFG_10_SET 0x0b4 |
| #define CLK_CFG_10_CLR 0x0b8 |
| #define CLK_CFG_11 0x0c0 |
| #define CLK_CFG_11_SET 0x0c4 |
| #define CLK_CFG_11_CLR 0x0c8 |
| #define CLK_CFG_12 0x0d0 |
| #define CLK_CFG_12_SET 0x0d4 |
| #define CLK_CFG_12_CLR 0x0d8 |
| #define CLK_CFG_13 0x0e0 |
| #define CLK_CFG_13_SET 0x0e4 |
| #define CLK_CFG_13_CLR 0x0e8 |
| #define CLK_CFG_14 0x0f0 |
| #define CLK_CFG_14_SET 0x0f4 |
| #define CLK_CFG_14_CLR 0x0f8 |
| #define CLK_CFG_15 0x100 |
| #define CLK_CFG_15_SET 0x104 |
| #define CLK_CFG_15_CLR 0x108 |
| #define CLK_CFG_16 0x110 |
| #define CLK_CFG_16_SET 0x114 |
| #define CLK_CFG_16_CLR 0x118 |
| |
| /* SCP_ADSP */ |
| #define SCP_ADSP_CK_CG 1 |
| #define SCP_ADSP_NR_CLK 2 |
| |
| /* SCP_SYS */ |
| #define SCP_SYS_MD1 1 |
| #define SCP_SYS_CONN 2 |
| #define SCP_SYS_MFG0 3 |
| #define SCP_SYS_MFG1 4 |
| #define SCP_SYS_MFG2 5 |
| #define SCP_SYS_MFG3 6 |
| #define SCP_SYS_MFG4 7 |
| #define SCP_SYS_MFG5 8 |
| #define SCP_SYS_MFG6 9 |
| #define SCP_SYS_ISP 10 |
| #define SCP_SYS_ISP2 11 |
| #define SCP_SYS_IPE 12 |
| #define SCP_SYS_VDEC 13 |
| #define SCP_SYS_VDEC2 14 |
| #define SCP_SYS_VENC 15 |
| #define SCP_SYS_MDP 16 |
| #define SCP_SYS_DIS 17 |
| #define SCP_SYS_AUDIO 18 |
| #define SCP_SYS_ADSP 19 |
| #define SCP_SYS_CAM 20 |
| #define SCP_SYS_CAM_RAWA 21 |
| #define SCP_SYS_CAM_RAWB 22 |
| #define SCP_SYS_CAM_RAWC 23 |
| #define SCP_SYS_DP_TX 24 |
| #define SCP_SYS_MSDC 25 |
| #define SCP_SYS_VPU 26 |
| #define SCP_NR_SYSS 27 |
| |
| /* MDPSYS_CONFIG */ |
| #define MDP_MDP_RDMA0 1 |
| #define MDP_MDP_TDSHP0 2 |
| #define MDP_IMG_DL_ASYNC0 3 |
| #define MDP_IMG_DL_ASYNC1 4 |
| #define MDP_MDP_RDMA1 5 |
| #define MDP_MDP_TDSHP1 6 |
| #define MDP_SMI0 7 |
| #define MDP_APB_BUS 8 |
| #define MDP_MDP_WROT0 9 |
| #define MDP_MDP_RSZ0 10 |
| #define MDP_MDP_HDR0 11 |
| #define MDP_MDP_MUTEX0 12 |
| #define MDP_MDP_WROT1 13 |
| #define MDP_MDP_RSZ1 14 |
| #define MDP_MDP_HDR1 15 |
| #define MDP_MDP_FAKE_ENG0 16 |
| #define MDP_MDP_AAL0 17 |
| #define MDP_MDP_AAL1 18 |
| #define MDP_MDP_COLOR0 19 |
| #define MDP_MDP_COLOR1 20 |
| #define MDP_IMG_DL_RELAY0_ASYNC0 21 |
| #define MDP_IMG_DL_RELAY1_ASYNC1 22 |
| #define MDP_NR_CLK 23 |