arch/arm/boot/dts/mt2701.dtsi - LeafOS-Devices/android_kernel_realme_mt6785 - Gitiles

 /*
  * Copyright (c) 2015 MediaTek Inc.
  * Author: Erin.Lo <erin.lo@mediatek.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */

 #include <dt-bindings/clock/mt2701-clk.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt2701-power.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/memory/mt2701-larb-port.h>
 #include <dt-bindings/reset/mt2701-resets.h>
 #include "skeleton64.dtsi"
 #include "mt2701-pinfunc.h"

 / {
 	compatible = "mediatek,mt2701";
 	interrupt-parent = <&cirq>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		enable-method = "mediatek,mt81xx-tz-smp";

 		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
 		};
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x1>;
 		};
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x2>;
 		};
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x3>;
 		};
 	};

 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		trustzone-bootinfo@80002000 {
 			compatible = "mediatek,trustzone-bootinfo";
 			reg = <0 0x80002000 0 0x1000>;
 		};
 	};

 	system_clk: dummy13m {
 		compatible = "fixed-clock";
 		clock-frequency = <13000000>;
 		#clock-cells = <0>;
 	};

 	rtc_clk: dummy32k {
 		compatible = "fixed-clock";
 		clock-frequency = <32000>;
 		#clock-cells = <0>;
 	};

 	clk26m: oscillator@0 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <26000000>;
 		clock-output-names = "clk26m";
 	};

 	rtc32k: oscillator@1 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <32000>;
 		clock-output-names = "rtc32k";
 	};

 	thermal-zones {
 		cpu_thermal: cpu_thermal {
 			polling-delay-passive = <1000>; /* milliseconds */
 			polling-delay = <1000>; /* milliseconds */

 			thermal-sensors = <&thermal 0>;
 			sustainable-power = <1000>;

 			trips {
 				threshold: trip-point@0 {
 					temperature = <68000>;
 					hysteresis = <2000>;
 					type = "passive";
 				};

 				target: trip-point@1 {
 					temperature = <85000>;
 					hysteresis = <2000>;
 					type = "passive";
 				};

 				cpu_crit: cpu_crit@0 {
 					temperature = <115000>;
 					hysteresis = <2000>;
 					type = "critical";
 				};
 			};
 		};
 	};

 	timer {
 		compatible = "arm,armv7-timer";
 		interrupt-parent = <&gic>;
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};

 	topckgen: syscon@10000000 {
 		compatible = "mediatek,mt2701-topckgen", "syscon";
 		reg = <0 0x10000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	infracfg: syscon@10001000 {
 		compatible = "mediatek,mt2701-infracfg", "syscon";
 		reg = <0 0x10001000 0 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};

 	pericfg: syscon@10003000 {
 		compatible = "mediatek,mt2701-pericfg", "syscon";
 		reg = <0 0x10003000 0 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};

 	syscfg_pctl_a: syscfg@10005000 {
 		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
 		reg = <0 0x10005000 0 0x1000>;
 	};

 	scpsys: scpsys@10006000 {
 		compatible = "mediatek,mt2701-scpsys", "syscon";
 		#power-domain-cells = <1>;
 		reg = <0 0x10006000 0 0x1000>;
 		infracfg = <&infracfg>;
 		clocks = <&topckgen CLK_TOP_MM_SEL>,
 			 <&topckgen CLK_TOP_MFG_SEL>,
 			 <&topckgen CLK_TOP_ETHIF_SEL>;
 		clock-names = "mm", "mfg", "ethif";
 	};

 	watchdog: watchdog@10007000 {
 		compatible = "mediatek,mt2701-wdt",
 			     "mediatek,mt6589-wdt";
 		reg = <0 0x10007000 0 0x100>;
 	};

 	timer: timer@10008000 {
 		compatible = "mediatek,mt2701-timer",
 			     "mediatek,mt6577-timer";
 		reg = <0 0x10008000 0 0x80>;
 		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&system_clk>, <&rtc_clk>;
 		clock-names = "system-clk", "rtc-clk";
 	};

 	pio: pinctrl@1000b000 {
 		compatible = "mediatek,mt2701-pinctrl";
 		reg = <0 0x1000b000 0 0x1000>;
 		mediatek,pctl-regmap = <&syscfg_pctl_a>;
 		pins-are-numbered;
 		gpio-controller;
 		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 	};

 	smi_common: smi@1000c000 {
 		compatible = "mediatek,mt2701-smi-common";
 		reg = <0 0x1000c000 0 0x1000>;
 		clocks = <&infracfg CLK_INFRA_SMI>,
 			 <&mmsys CLK_MM_SMI_COMMON>,
 			 <&infracfg CLK_INFRA_SMI>;
 		clock-names = "apb", "smi", "async";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 	};

 	sysirq: interrupt-controller@10200100 {
 		compatible = "mediatek,mt2701-sysirq",
 			     "mediatek,mt6577-sysirq";
 		interrupt-controller;
 		#interrupt-cells = <3>;
 		interrupt-parent = <&gic>;
 		reg = <0 0x10200100 0 0x1c>;
 	};

 	cirq: interrupt-controller@10204000 {
 		compatible = "mediatek,mt2701-cirq",
 			     "mediatek,mtk-cirq";
 		interrupt-controller;
 		#interrupt-cells = <3>;
 		interrupt-parent = <&sysirq>;
 		reg = <0 0x10204000 0 0x400>;
 		mediatek,ext-irq-range = <32 200>;
 	};

 	iommu: mmsys_iommu@10205000 {
 		compatible = "mediatek,mt2701-m4u";
 		reg = <0 0x10205000 0 0x1000>;
 		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&infracfg CLK_INFRA_M4U>;
 		clock-names = "bclk";
 		mediatek,larbs = <&larb0 &larb1 &larb2>;
 		#iommu-cells = <1>;
 	};

 	apmixedsys: syscon@10209000 {
 		compatible = "mediatek,mt2701-apmixedsys", "syscon";
 		reg = <0 0x10209000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	gic: interrupt-controller@10211000 {
 		compatible = "arm,cortex-a7-gic";
 		interrupt-controller;
 		#interrupt-cells = <3>;
 		interrupt-parent = <&gic>;
 		reg = <0 0x10211000 0 0x1000>,
 		      <0 0x10212000 0 0x2000>,
 		      <0 0x10214000 0 0x2000>,
 		      <0 0x10216000 0 0x2000>;
 	};

 	auxadc: adc@11001000 {
 		compatible = "mediatek,mt2701-auxadc";
 		reg = <0 0x11001000 0 0x1000>;
 		clocks = <&pericfg CLK_PERI_AUXADC>;
 		clock-names = "main";
 		#io-channel-cells = <1>;
 		status = "disabled";
 	};

 	uart0: serial@11002000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11002000 0 0x400>;
 		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 		clock-names = "baud", "bus";
 		status = "disabled";
 	};

 	uart1: serial@11003000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11003000 0 0x400>;
 		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 		clock-names = "baud", "bus";
 		status = "disabled";
 	};

 	uart2: serial@11004000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11004000 0 0x400>;
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 		clock-names = "baud", "bus";
 		status = "disabled";
 	};

 	uart3: serial@11005000 {
 		compatible = "mediatek,mt2701-uart",
 			     "mediatek,mt6577-uart";
 		reg = <0 0x11005000 0 0x400>;
 		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 		clock-names = "baud", "bus";
 		status = "disabled";
 	};

 	i2c0: i2c@11007000 {
 		compatible = "mediatek,mt2701-i2c",
 			     "mediatek,mt6577-i2c";
 		reg = <0 0x11007000 0 0x70>,
 		      <0 0x11000200 0 0x80>;
 		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 		clock-div = <16>;
 		clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
 		clock-names = "main", "dma";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};

 	i2c1: i2c@11008000 {
 		compatible = "mediatek,mt2701-i2c",
 			     "mediatek,mt6577-i2c";
 		reg = <0 0x11008000 0 0x70>,
 		      <0 0x11000280 0 0x80>;
 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 		clock-div = <16>;
 		clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
 		clock-names = "main", "dma";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};

 	i2c2: i2c@11009000 {
 		compatible = "mediatek,mt2701-i2c",
 			     "mediatek,mt6577-i2c";
 		reg = <0 0x11009000 0 0x70>,
 		      <0 0x11000300 0 0x80>;
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 		clock-div = <16>;
 		clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
 		clock-names = "main", "dma";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};

 	spi0: spi@1100a000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0 0x1100a000 0 0x100>;
 		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 			 <&topckgen CLK_TOP_SPI0_SEL>,
 			 <&pericfg CLK_PERI_SPI0>;
 		clock-names = "parent-clk", "sel-clk", "spi-clk";
 		status = "disabled";
 	};

 	thermal: thermal@1100b000 {
 		#thermal-sensor-cells = <0>;
 		compatible = "mediatek,mt2701-thermal";
 		reg = <0 0x1100b000 0 0x1000>;
 		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 		clock-names = "therm", "auxadc";
 		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 		reset-names = "therm";
 		mediatek,auxadc = <&auxadc>;
 		mediatek,apmixedsys = <&apmixedsys>;
 	};

 	nandc: nfi@1100d000 {
 		compatible = "mediatek,mt2701-nfc";
 		reg = <0 0x1100d000 0 0x1000>;
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_NFI>,
 			 <&pericfg CLK_PERI_NFI_PAD>;
 		clock-names = "nfi_clk", "pad_clk";
 		status = "disabled";
 		ecc-engine = <&bch>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 	};

 	bch: ecc@1100e000 {
 		compatible = "mediatek,mt2701-ecc";
 		reg = <0 0x1100e000 0 0x1000>;
 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&pericfg CLK_PERI_NFI_ECC>;
 		clock-names = "nfiecc_clk";
 		status = "disabled";
 	};

 	nor_flash: spi@11014000 {
 		compatible = "mediatek,mt2701-nor",
 			     "mediatek,mt8173-nor";
 		reg = <0 0x11014000 0 0xe0>;
 		clocks = <&pericfg CLK_PERI_FLASH>,
 			 <&topckgen CLK_TOP_FLASH_SEL>;
 		clock-names = "spi", "sf";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};

 	spi1: spi@11016000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0 0x11016000 0 0x100>;
 		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 			 <&topckgen CLK_TOP_SPI1_SEL>,
 			 <&pericfg CLK_PERI_SPI1>;
 		clock-names = "parent-clk", "sel-clk", "spi-clk";
 		status = "disabled";
 	};

 	spi2: spi@11017000 {
 		compatible = "mediatek,mt2701-spi";
 		#address-cells = <1>;
 		#size-cells = <0>;
 		reg = <0 0x11017000 0 0x1000>;
 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 			 <&topckgen CLK_TOP_SPI2_SEL>,
 			 <&pericfg CLK_PERI_SPI2>;
 		clock-names = "parent-clk", "sel-clk", "spi-clk";
 		status = "disabled";
 	};

 	afe: audio-controller@11220000 {
 		compatible = "mediatek,mt2701-audio";
 		reg = <0 0x11220000 0 0x2000>,
 		      <0 0x112a0000 0 0x20000>;
 		interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

 		clocks = <&infracfg CLK_INFRA_AUDIO>,
 			 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 			 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 			 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 			 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 			 <&topckgen CLK_TOP_AUD_48K_TIMING>,
 			 <&topckgen CLK_TOP_AUD_44K_TIMING>,
 			 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 			 <&topckgen CLK_TOP_APLL_SEL>,
 			 <&topckgen CLK_TOP_AUD1PLL_98M>,
 			 <&topckgen CLK_TOP_AUD2PLL_90M>,
 			 <&topckgen CLK_TOP_HADDS2PLL_98M>,
 			 <&topckgen CLK_TOP_HADDS2PLL_294M>,
 			 <&topckgen CLK_TOP_AUDPLL>,
 			 <&topckgen CLK_TOP_AUDPLL_D4>,
 			 <&topckgen CLK_TOP_AUDPLL_D8>,
 			 <&topckgen CLK_TOP_AUDPLL_D16>,
 			 <&topckgen CLK_TOP_AUDPLL_D24>,
 			 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 			 <&clk26m>,
 			 <&topckgen CLK_TOP_SYSPLL1_D4>,
 			 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 			 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 			 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 			 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 			 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 			 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 			 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 			 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 			 <&topckgen CLK_TOP_ASM_M_SEL>,
 			 <&topckgen CLK_TOP_ASM_H_SEL>,
 			 <&topckgen CLK_TOP_UNIVPLL2_D4>,
 			 <&topckgen CLK_TOP_UNIVPLL2_D2>,
 			 <&topckgen CLK_TOP_SYSPLL_D5>;

 		clock-names = "infra_sys_audio_clk",
 			 "top_audio_mux1_sel",
 			 "top_audio_mux2_sel",
 			 "top_audio_mux1_div",
 			 "top_audio_mux2_div",
 			 "top_audio_48k_timing",
 			 "top_audio_44k_timing",
 			 "top_audpll_mux_sel",
 			 "top_apll_sel",
 			 "top_aud1_pll_98M",
 			 "top_aud2_pll_90M",
 			 "top_hadds2_pll_98M",
 			 "top_hadds2_pll_294M",
 			 "top_audpll",
 			 "top_audpll_d4",
 			 "top_audpll_d8",
 			 "top_audpll_d16",
 			 "top_audpll_d24",
 			 "top_audintbus_sel",
 			 "clk_26m",
 			 "top_syspll1_d4",
 			 "top_aud_k1_src_sel",
 			 "top_aud_k2_src_sel",
 			 "top_aud_k3_src_sel",
 			 "top_aud_k4_src_sel",
 			 "top_aud_k5_src_sel",
 			 "top_aud_k6_src_sel",
 			 "top_aud_k1_src_div",
 			 "top_aud_k2_src_div",
 			 "top_aud_k3_src_div",
 			 "top_aud_k4_src_div",
 			 "top_aud_k5_src_div",
 			 "top_aud_k6_src_div",
 			 "top_aud_i2s1_mclk",
 			 "top_aud_i2s2_mclk",
 			 "top_aud_i2s3_mclk",
 			 "top_aud_i2s4_mclk",
 			 "top_aud_i2s5_mclk",
 			 "top_aud_i2s6_mclk",
 			 "top_asm_m_sel",
 			 "top_asm_h_sel",
 			 "top_univpll2_d4",
 			 "top_univpll2_d2",
 			 "top_syspll_d5";
 	};

 	mmsys: syscon@14000000 {
 		compatible = "mediatek,mt2701-mmsys", "syscon";
 		reg = <0 0x14000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	larb0: larb@14010000 {
 		compatible = "mediatek,mt2701-smi-larb";
 		reg = <0 0x14010000 0 0x1000>;
 		mediatek,smi = <&smi_common>;
 		mediatek,larb-id = <0>;
 		clocks = <&mmsys CLK_MM_SMI_LARB0>,
 			 <&mmsys CLK_MM_SMI_LARB0>;
 		clock-names = "apb", "smi";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
 	};

 	imgsys: syscon@15000000 {
 		compatible = "mediatek,mt2701-imgsys", "syscon";
 		reg = <0 0x15000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	larb2: larb@15001000 {
 		compatible = "mediatek,mt2701-smi-larb";
 		reg = <0 0x15001000 0 0x1000>;
 		mediatek,smi = <&smi_common>;
 		mediatek,larb-id = <2>;
 		clocks = <&imgsys CLK_IMG_SMI_COMM>,
 			 <&imgsys CLK_IMG_SMI_COMM>;
 		clock-names = "apb", "smi";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 	};

 	jpegdec: jpegdec@15004000 {
 		compatible = "mediatek,mt2701-jpgdec";
 		reg = <0 0x15004000 0 0x1000>;
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
 		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
 			  <&imgsys CLK_IMG_JPGDEC>;
 		clock-names = "jpgdec-smi",
 			      "jpgdec";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
 		mediatek,larb = <&larb2>;
 		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
 			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
 	};

 	vdecsys: syscon@16000000 {
 		compatible = "mediatek,mt2701-vdecsys", "syscon";
 		reg = <0 0x16000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	larb1: larb@16010000 {
 		compatible = "mediatek,mt2701-smi-larb";
 		reg = <0 0x16010000 0 0x1000>;
 		mediatek,smi = <&smi_common>;
 		mediatek,larb-id = <1>;
 		clocks = <&vdecsys CLK_VDEC_CKGEN>,
 			 <&vdecsys CLK_VDEC_LARB>;
 		clock-names = "apb", "smi";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
 	};

 	hifsys: syscon@1a000000 {
 		compatible = "mediatek,mt2701-hifsys", "syscon";
 		reg = <0 0x1a000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	usb0: usb@1a1c0000 {
 		compatible = "mediatek,mt8173-xhci";
 		reg = <0 0x1a1c0000 0 0x1000>,
 		      <0 0x1a1c4700 0 0x0100>;
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 			 <&topckgen CLK_TOP_ETHIF_SEL>;
 		clock-names = "sys_ck", "ref_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 		status = "disabled";
 	};

 	u3phy0: usb-phy@1a1c4000 {
 		compatible = "mediatek,mt2701-u3phy";
 		reg = <0 0x1a1c4000 0 0x0700>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 		status = "disabled";

 		u2port0: usb-phy@1a1c4800 {
 			reg = <0 0x1a1c4800 0 0x0100>;
 			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};

 		u3port0: usb-phy@1a1c4900 {
 			reg = <0 0x1a1c4900 0 0x0700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 	};

 	usb1: usb@1a240000 {
 		compatible = "mediatek,mt8173-xhci";
 		reg = <0 0x1a240000 0 0x1000>,
 		      <0 0x1a244700 0 0x0100>;
 		reg-names = "mac", "ippc";
 		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 			 <&topckgen CLK_TOP_ETHIF_SEL>;
 		clock-names = "sys_ck", "ref_ck";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 		status = "disabled";
 	};

 	u3phy1: usb-phy@1a244000 {
 		compatible = "mediatek,mt2701-u3phy";
 		reg = <0 0x1a244000 0 0x0700>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 		status = "disabled";

 		u2port1: usb-phy@1a244800 {
 			reg = <0 0x1a244800 0 0x0100>;
 			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};

 		u3port1: usb-phy@1a244900 {
 			reg = <0 0x1a244900 0 0x0700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 	};

 	ethsys: syscon@1b000000 {
 		compatible = "mediatek,mt2701-ethsys", "syscon";
 		reg = <0 0x1b000000 0 0x1000>;
 		#clock-cells = <1>;
 	};

 	eth: ethernet@1b100000 {
 		compatible = "mediatek,mt2701-eth", "syscon";
 		reg = <0 0x1b100000 0 0x20000>;
 		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 			 <&ethsys CLK_ETHSYS_ESW>,
 			 <&ethsys CLK_ETHSYS_GP1>,
 			 <&ethsys CLK_ETHSYS_GP2>,
 			 <&apmixedsys CLK_APMIXED_TRGPLL>;
 		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
 			 <&ethsys MT2701_ETHSYS_PPE_RST>;
 		reset-names = "fe", "gmac", "ppe";
 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 		mediatek,ethsys = <&ethsys>;
 		mediatek,pctl = <&syscfg_pctl_a>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
 	};

 	bdpsys: syscon@1c000000 {
 		compatible = "mediatek,mt2701-bdpsys", "syscon";
 		reg = <0 0x1c000000 0 0x1000>;
 		#clock-cells = <1>;
 	};
 };
	/*
	* Copyright (c) 2015 MediaTek Inc.
	* Author: Erin.Lo <erin.lo@mediatek.com>
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/

	#include <dt-bindings/clock/mt2701-clk.h>
	#include <dt-bindings/phy/phy.h>
	#include <dt-bindings/power/mt2701-power.h>
	#include <dt-bindings/interrupt-controller/irq.h>
	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/memory/mt2701-larb-port.h>
	#include <dt-bindings/reset/mt2701-resets.h>
	#include "skeleton64.dtsi"
	#include "mt2701-pinfunc.h"

	/ {
	compatible = "mediatek,mt2701";
	interrupt-parent = <&cirq>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;
	enable-method = "mediatek,mt81xx-tz-smp";

	cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x0>;
	};
	cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x1>;
	};
	cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x2>;
	};
	cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a7";
	reg = <0x3>;
	};
	};

	reserved-memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	trustzone-bootinfo@80002000 {
	compatible = "mediatek,trustzone-bootinfo";
	reg = <0 0x80002000 0 0x1000>;
	};
	};

	system_clk: dummy13m {
	compatible = "fixed-clock";
	clock-frequency = <13000000>;
	#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <26000000>;
	clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <32000>;
	clock-output-names = "rtc32k";
	};

	thermal-zones {
	cpu_thermal: cpu_thermal {
	polling-delay-passive = <1000>; /* milliseconds */
	polling-delay = <1000>; /* milliseconds */

	thermal-sensors = <&thermal 0>;
	sustainable-power = <1000>;

	trips {
	threshold: trip-point@0 {
	temperature = <68000>;
	hysteresis = <2000>;
	type = "passive";
	};

	target: trip-point@1 {
	temperature = <85000>;
	hysteresis = <2000>;
	type = "passive";
	};

	cpu_crit: cpu_crit@0 {
	temperature = <115000>;
	hysteresis = <2000>;
	type = "critical";
	};
	};
	};
	};

	timer {
	compatible = "arm,armv7-timer";
	interrupt-parent = <&gic>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
	compatible = "mediatek,mt2701-topckgen", "syscon";
	reg = <0 0x10000000 0 0x1000>;
	#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
	compatible = "mediatek,mt2701-infracfg", "syscon";
	reg = <0 0x10001000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
	compatible = "mediatek,mt2701-pericfg", "syscon";
	reg = <0 0x10003000 0 0x1000>;
	#clock-cells = <1>;
	#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: scpsys@10006000 {
	compatible = "mediatek,mt2701-scpsys", "syscon";
	#power-domain-cells = <1>;
	reg = <0 0x10006000 0 0x1000>;
	infracfg = <&infracfg>;
	clocks = <&topckgen CLK_TOP_MM_SEL>,
	<&topckgen CLK_TOP_MFG_SEL>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
	compatible = "mediatek,mt2701-wdt",
	"mediatek,mt6589-wdt";
	reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
	compatible = "mediatek,mt2701-timer",
	"mediatek,mt6577-timer";
	reg = <0 0x10008000 0 0x80>;
	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&system_clk>, <&rtc_clk>;
	clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
	compatible = "mediatek,mt2701-pinctrl";
	reg = <0 0x1000b000 0 0x1000>;
	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	pins-are-numbered;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
	compatible = "mediatek,mt2701-smi-common";
	reg = <0 0x1000c000 0 0x1000>;
	clocks = <&infracfg CLK_INFRA_SMI>,
	<&mmsys CLK_MM_SMI_COMMON>,
	<&infracfg CLK_INFRA_SMI>;
	clock-names = "apb", "smi", "async";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
	compatible = "mediatek,mt2701-sysirq",
	"mediatek,mt6577-sysirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10200100 0 0x1c>;
	};

	cirq: interrupt-controller@10204000 {
	compatible = "mediatek,mt2701-cirq",
	"mediatek,mtk-cirq";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&sysirq>;
	reg = <0 0x10204000 0 0x400>;
	mediatek,ext-irq-range = <32 200>;
	};

	iommu: mmsys_iommu@10205000 {
	compatible = "mediatek,mt2701-m4u";
	reg = <0 0x10205000 0 0x1000>;
	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&infracfg CLK_INFRA_M4U>;
	clock-names = "bclk";
	mediatek,larbs = <&larb0 &larb1 &larb2>;
	#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
	compatible = "mediatek,mt2701-apmixedsys", "syscon";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
	compatible = "arm,cortex-a7-gic";
	interrupt-controller;
	#interrupt-cells = <3>;
	interrupt-parent = <&gic>;
	reg = <0 0x10211000 0 0x1000>,
	<0 0x10212000 0 0x2000>,
	<0 0x10214000 0 0x2000>,
	<0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
	compatible = "mediatek,mt2701-auxadc";
	reg = <0 0x11001000 0 0x1000>;
	clocks = <&pericfg CLK_PERI_AUXADC>;
	clock-names = "main";
	#io-channel-cells = <1>;
	status = "disabled";
	};

	uart0: serial@11002000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11002000 0 0x400>;
	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart1: serial@11003000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11003000 0 0x400>;
	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart2: serial@11004000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11004000 0 0x400>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	uart3: serial@11005000 {
	compatible = "mediatek,mt2701-uart",
	"mediatek,mt6577-uart";
	reg = <0 0x11005000 0 0x400>;
	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
	clock-names = "baud", "bus";
	status = "disabled";
	};

	i2c0: i2c@11007000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11007000 0 0x70>,
	<0 0x11000200 0 0x80>;
	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c1: i2c@11008000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11008000 0 0x70>,
	<0 0x11000280 0 0x80>;
	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	i2c2: i2c@11009000 {
	compatible = "mediatek,mt2701-i2c",
	"mediatek,mt6577-i2c";
	reg = <0 0x11009000 0 0x70>,
	<0 0x11000300 0 0x80>;
	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
	clock-div = <16>;
	clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
	clock-names = "main", "dma";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi0: spi@1100a000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x1100a000 0 0x100>;
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI0_SEL>,
	<&pericfg CLK_PERI_SPI0>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	thermal: thermal@1100b000 {
	#thermal-sensor-cells = <0>;
	compatible = "mediatek,mt2701-thermal";
	reg = <0 0x1100b000 0 0x1000>;
	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	clock-names = "therm", "auxadc";
	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	reset-names = "therm";
	mediatek,auxadc = <&auxadc>;
	mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
	compatible = "mediatek,mt2701-nfc";
	reg = <0 0x1100d000 0 0x1000>;
	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI>,
	<&pericfg CLK_PERI_NFI_PAD>;
	clock-names = "nfi_clk", "pad_clk";
	status = "disabled";
	ecc-engine = <&bch>;
	#address-cells = <1>;
	#size-cells = <0>;
	};

	bch: ecc@1100e000 {
	compatible = "mediatek,mt2701-ecc";
	reg = <0 0x1100e000 0 0x1000>;
	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	clock-names = "nfiecc_clk";
	status = "disabled";
	};

	nor_flash: spi@11014000 {
	compatible = "mediatek,mt2701-nor",
	"mediatek,mt8173-nor";
	reg = <0 0x11014000 0 0xe0>;
	clocks = <&pericfg CLK_PERI_FLASH>,
	<&topckgen CLK_TOP_FLASH_SEL>;
	clock-names = "spi", "sf";
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	spi1: spi@11016000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11016000 0 0x100>;
	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI1_SEL>,
	<&pericfg CLK_PERI_SPI1>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	spi2: spi@11017000 {
	compatible = "mediatek,mt2701-spi";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0 0x11017000 0 0x1000>;
	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	<&topckgen CLK_TOP_SPI2_SEL>,
	<&pericfg CLK_PERI_SPI2>;
	clock-names = "parent-clk", "sel-clk", "spi-clk";
	status = "disabled";
	};

	afe: audio-controller@11220000 {
	compatible = "mediatek,mt2701-audio";
	reg = <0 0x11220000 0 0x2000>,
	<0 0x112a0000 0 0x20000>;
	interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

	clocks = <&infracfg CLK_INFRA_AUDIO>,
	<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
	<&topckgen CLK_TOP_AUD_MUX2_DIV>,
	<&topckgen CLK_TOP_AUD_48K_TIMING>,
	<&topckgen CLK_TOP_AUD_44K_TIMING>,
	<&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
	<&topckgen CLK_TOP_APLL_SEL>,
	<&topckgen CLK_TOP_AUD1PLL_98M>,
	<&topckgen CLK_TOP_AUD2PLL_90M>,
	<&topckgen CLK_TOP_HADDS2PLL_98M>,
	<&topckgen CLK_TOP_HADDS2PLL_294M>,
	<&topckgen CLK_TOP_AUDPLL>,
	<&topckgen CLK_TOP_AUDPLL_D4>,
	<&topckgen CLK_TOP_AUDPLL_D8>,
	<&topckgen CLK_TOP_AUDPLL_D16>,
	<&topckgen CLK_TOP_AUDPLL_D24>,
	<&topckgen CLK_TOP_AUDINTBUS_SEL>,
	<&clk26m>,
	<&topckgen CLK_TOP_SYSPLL1_D4>,
	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S5_MCLK>,
	<&topckgen CLK_TOP_AUD_I2S6_MCLK>,
	<&topckgen CLK_TOP_ASM_M_SEL>,
	<&topckgen CLK_TOP_ASM_H_SEL>,
	<&topckgen CLK_TOP_UNIVPLL2_D4>,
	<&topckgen CLK_TOP_UNIVPLL2_D2>,
	<&topckgen CLK_TOP_SYSPLL_D5>;

	clock-names = "infra_sys_audio_clk",
	"top_audio_mux1_sel",
	"top_audio_mux2_sel",
	"top_audio_mux1_div",
	"top_audio_mux2_div",
	"top_audio_48k_timing",
	"top_audio_44k_timing",
	"top_audpll_mux_sel",
	"top_apll_sel",
	"top_aud1_pll_98M",
	"top_aud2_pll_90M",
	"top_hadds2_pll_98M",
	"top_hadds2_pll_294M",
	"top_audpll",
	"top_audpll_d4",
	"top_audpll_d8",
	"top_audpll_d16",
	"top_audpll_d24",
	"top_audintbus_sel",
	"clk_26m",
	"top_syspll1_d4",
	"top_aud_k1_src_sel",
	"top_aud_k2_src_sel",
	"top_aud_k3_src_sel",
	"top_aud_k4_src_sel",
	"top_aud_k5_src_sel",
	"top_aud_k6_src_sel",
	"top_aud_k1_src_div",
	"top_aud_k2_src_div",
	"top_aud_k3_src_div",
	"top_aud_k4_src_div",
	"top_aud_k5_src_div",
	"top_aud_k6_src_div",
	"top_aud_i2s1_mclk",
	"top_aud_i2s2_mclk",
	"top_aud_i2s3_mclk",
	"top_aud_i2s4_mclk",
	"top_aud_i2s5_mclk",
	"top_aud_i2s6_mclk",
	"top_asm_m_sel",
	"top_asm_h_sel",
	"top_univpll2_d4",
	"top_univpll2_d2",
	"top_syspll_d5";
	};

	mmsys: syscon@14000000 {
	compatible = "mediatek,mt2701-mmsys", "syscon";
	reg = <0 0x14000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb0: larb@14010000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x14010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <0>;
	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	<&mmsys CLK_MM_SMI_LARB0>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
	compatible = "mediatek,mt2701-imgsys", "syscon";
	reg = <0 0x15000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb2: larb@15001000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x15001000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <2>;
	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	<&imgsys CLK_IMG_SMI_COMM>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
	compatible = "mediatek,mt2701-jpgdec";
	reg = <0 0x15004000 0 0x1000>;
	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
	<&imgsys CLK_IMG_JPGDEC>;
	clock-names = "jpgdec-smi",
	"jpgdec";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	mediatek,larb = <&larb2>;
	iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
	<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
	compatible = "mediatek,mt2701-vdecsys", "syscon";
	reg = <0 0x16000000 0 0x1000>;
	#clock-cells = <1>;
	};

	larb1: larb@16010000 {
	compatible = "mediatek,mt2701-smi-larb";
	reg = <0 0x16010000 0 0x1000>;
	mediatek,smi = <&smi_common>;
	mediatek,larb-id = <1>;
	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	<&vdecsys CLK_VDEC_LARB>;
	clock-names = "apb", "smi";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
	compatible = "mediatek,mt2701-hifsys", "syscon";
	reg = <0 0x1a000000 0 0x1000>;
	#clock-cells = <1>;
	};

	usb0: usb@1a1c0000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x1a1c0000 0 0x1000>,
	<0 0x1a1c4700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy0: usb-phy@1a1c4000 {
	compatible = "mediatek,mt2701-u3phy";
	reg = <0 0x1a1c4000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port0: usb-phy@1a1c4800 {
	reg = <0 0x1a1c4800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port0: usb-phy@1a1c4900 {
	reg = <0 0x1a1c4900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	usb1: usb@1a240000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x1a240000 0 0x1000>,
	<0 0x1a244700 0 0x0100>;
	reg-names = "mac", "ippc";
	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
	<&topckgen CLK_TOP_ETHIF_SEL>;
	clock-names = "sys_ck", "ref_ck";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
	status = "disabled";
	};

	u3phy1: usb-phy@1a244000 {
	compatible = "mediatek,mt2701-u3phy";
	reg = <0 0x1a244000 0 0x0700>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;
	status = "disabled";

	u2port1: usb-phy@1a244800 {
	reg = <0 0x1a244800 0 0x0100>;
	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};

	u3port1: usb-phy@1a244900 {
	reg = <0 0x1a244900 0 0x0700>;
	clocks = <&clk26m>;
	clock-names = "ref";
	#phy-cells = <1>;
	status = "okay";
	};
	};

	ethsys: syscon@1b000000 {
	compatible = "mediatek,mt2701-ethsys", "syscon";
	reg = <0 0x1b000000 0 0x1000>;
	#clock-cells = <1>;
	};

	eth: ethernet@1b100000 {
	compatible = "mediatek,mt2701-eth", "syscon";
	reg = <0 0x1b100000 0 0x20000>;
	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
	<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	<&ethsys CLK_ETHSYS_ESW>,
	<&ethsys CLK_ETHSYS_GP1>,
	<&ethsys CLK_ETHSYS_GP2>,
	<&apmixedsys CLK_APMIXED_TRGPLL>;
	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	resets = <&ethsys MT2701_ETHSYS_FE_RST>,
	<&ethsys MT2701_ETHSYS_GMAC_RST>,
	<&ethsys MT2701_ETHSYS_PPE_RST>;
	reset-names = "fe", "gmac", "ppe";
	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	mediatek,ethsys = <&ethsys>;
	mediatek,pctl = <&syscfg_pctl_a>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	bdpsys: syscon@1c000000 {
	compatible = "mediatek,mt2701-bdpsys", "syscon";
	reg = <0 0x1c000000 0 0x1000>;
	#clock-cells = <1>;
	};
	};