| # |
| # Performance Monitor Drivers |
| # |
| |
| menu "Performance monitor support" |
| depends on PERF_EVENTS |
| |
| config ARM_PMU |
| depends on ARM || ARM64 |
| bool "ARM PMU framework" |
| default y |
| help |
| Say y if you want to use CPU performance monitors on ARM-based |
| systems. |
| |
| config ARM_PMU_ACPI |
| depends on ARM_PMU && ACPI |
| def_bool y |
| |
| config ARM_DSU_PMU |
| tristate "ARM DynamIQ Shared Unit (DSU) PMU" |
| depends on ARM64 && PERF_EVENTS |
| help |
| Provides support for performance monitor unit in ARM DynamIQ Shared |
| Unit (DSU). The DSU integrates one or more cores with an L3 memory |
| system, control logic. The PMU allows counting various events related |
| to DSU. |
| |
| config QCOM_L2_PMU |
| bool "Qualcomm Technologies L2-cache PMU" |
| depends on ARCH_QCOM && ARM64 && ACPI |
| help |
| Provides support for the L2 cache performance monitor unit (PMU) |
| in Qualcomm Technologies processors. |
| Adds the L2 cache PMU into the perf events subsystem for |
| monitoring L2 cache events. |
| |
| config QCOM_L3_PMU |
| bool "Qualcomm Technologies L3-cache PMU" |
| depends on ARCH_QCOM && ARM64 && ACPI |
| select QCOM_IRQ_COMBINER |
| help |
| Provides support for the L3 cache performance monitor unit (PMU) |
| in Qualcomm Technologies processors. |
| Adds the L3 cache PMU into the perf events subsystem for |
| monitoring L3 cache events. |
| |
| config XGENE_PMU |
| depends on ARCH_XGENE |
| bool "APM X-Gene SoC PMU" |
| default n |
| help |
| Say y if you want to use APM X-Gene SoC performance monitors. |
| |
| endmenu |