tree 2a1dea95ca2d50192216500d90d9b0358af1dc1d
parent 59fcf48fdebe65e4774d2c7ec76b7845d281749a
author Kirill A. Shutemov <kirill@shutemov.name> 1253006633 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1253048798 +0100

ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size

Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>