OMAP4 powerdomain: Support LOWPOWERSTATECHANGE for powerdomains
Some powerdomains in OMAP4 support a direct transition from one sleep
state to another deeper sleep state without having to wakeup the
powerdomain. This patch adds an api in the powerdomain framework to
set the LOWPOWERSTATECHANGE bit in PWRSTCTRL register.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index ad5a265..c721951 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -54,6 +54,7 @@
[3] = PWRDM_POWER_ON, /* ducati_l2ram */
[4] = PWRDM_POWER_ON, /* ducati_unicache */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -69,6 +70,7 @@
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* gfx_mem */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* abe_44xx_pwrdm: Audio back end power domain */
@@ -87,6 +89,7 @@
[0] = PWRDM_POWER_ON, /* aessmem */
[1] = PWRDM_POWER_ON, /* periphmem */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -103,6 +106,7 @@
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* dss_mem */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -123,6 +127,7 @@
[1] = PWRDM_POWER_ON, /* tesla_l1 */
[2] = PWRDM_POWER_ON, /* tesla_l2 */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -227,6 +232,7 @@
[2] = PWRDM_POWER_ON, /* tcm1_mem */
[3] = PWRDM_POWER_ON, /* tcm2_mem */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -242,6 +248,7 @@
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* cam_mem */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -258,6 +265,7 @@
.pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* l3init_bank1 */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -276,6 +284,7 @@
[0] = PWRDM_POWER_ON, /* nonretained_bank */
[1] = PWRDM_POWER_ON, /* retained_bank */
},
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*