commit 852c15b7362cf34e0d7949abefbfeeb0845d93b4
author David Howells <dhowells@redhat.com> Wed Nov 12 15:35:40 2008 +0000
committer Linus Torvalds <torvalds@linux-foundation.org> Wed Nov 12 10:41:17 2008 -0800
tree 98dade6ff2f502d65c29f6e7df8bd4032c1578bf
parent 6d615c78fb92fbd80e52ba7acb2d4c4d503006c3

MN10300: Fix misaligned index-register addressing handling

Fix misalignment handling for an address calculated from the sum of two
registers.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

arch/mn10300/mm/misalignment.c

diff --git a/arch/mn10300/mm/misalignment.c b/arch/mn10300/mm/misalignment.c
index 61e65ec..a598368 100644
--- a/arch/mn10300/mm/misalignment.c
+++ b/arch/mn10300/mm/misalignment.c
@@ -570,11 +570,11 @@
 			address += *postinc;
 			break;
 		case DM1:
-			postinc = &registers[Dreg_index[opcode >> 2 & 0x0c]];
+			postinc = &registers[Dreg_index[opcode >> 2 & 0x03]];
 			address += *postinc;
 			break;
 		case DM2:
-			postinc = &registers[Dreg_index[opcode >> 4 & 0x30]];
+			postinc = &registers[Dreg_index[opcode >> 4 & 0x03]];
 			address += *postinc;
 			break;
 		case AM0:
@@ -582,11 +582,11 @@
 			address += *postinc;
 			break;
 		case AM1:
-			postinc = &registers[Areg_index[opcode >> 2 & 0x0c]];
+			postinc = &registers[Areg_index[opcode >> 2 & 0x03]];
 			address += *postinc;
 			break;
 		case AM2:
-			postinc = &registers[Areg_index[opcode >> 4 & 0x30]];
+			postinc = &registers[Areg_index[opcode >> 4 & 0x03]];
 			address += *postinc;
 			break;
 		case RM0: