tree a1c3ef94f0829eccd4b1e03429a35cef3466fb2d
parent e80cf2e50bfabb14dd3667b2360a393dda3edc3f
author Maxime Ripard <maxime.ripard@free-electrons.com> 1448968492 +0100
committer Stephen Boyd <sboyd@codeaurora.org> 1449127667 -0800

clk: sunxi: pll2: Fix clock running too fast

Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.

This fixes the audio playing too fast.

Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>